參數(shù)資料
型號(hào)： TLV5638D
廠商： Texas Instruments, Inc.
英文描述： 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
中文描述： 2.7 V至5.5 V低功耗雙通道12位數(shù)字至模擬轉(zhuǎn)換器，具有內(nèi)部參考和斷電
文件頁(yè)數(shù)： 6/19頁(yè)
文件大?。?/td> 289K
代理商： TLV5638D
TLV5638
2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS225A – JUNE 1999 – REVISED JANUARY 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
μ
A
pF
IIH
IIL
Ci
High-level digital input current
VI = VDD
VI = 0 V
1
Low-level digital input current
–1
Input capacitance
8
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t(FS)
ts(FS)
Output settling time full scale
Output settling time, full scale
RL = 10 k
See Note 11
CL = 100 pF,
Fast
1
3
μ
s
,
Slow
3.5
7
t(CC)
ts(CC)
Output settling time code to code
Output settling time, code to code
RL = 10 k
See Note 12
CL = 100 pF,
Fast
0.5
1.5
μ
s
,
Slow
1
2
SR
Slew rate
RL = 10 k
See Note 13
CL = 100 pF,
Fast
12
V/
μ
s
,
Slow
1.8
Glitch energy
DIN = 0 to 1,
CS = VDD
FCLK = 100 kHz,
5
nV–s
SNR
Signal-to-noise ratio
69
74
S/(N+D)
Signal-to-noise + distortion
fs = 480 kSPS, fout
RL = 10 k
,
58
67
dB
THD
Total harmonic distortion
CL = 100 pF
,
–69
–57
Spurious free dynamic range
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
57
72
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CS–CK)
tsu(C16-CS)
twH
twL
tsu(D)
th(D)
Setup time, CS low before first negative SCLK edge
Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge
10
ns
10
ns
SCLK pulse width high
25
ns
SCLK pulse width low
25
ns
Setup time, data ready before SCLK falling edge
10
ns
Hold time, data held valid after SCLK falling edge
5
ns
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