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參數(shù)資料
| 型號： | TLV5632IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大小： | 511K |
| 代理商： | TLV5632IPWRG4 |
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
www.ti.com .................................................................................................................................................... SLAS269F – MAY 2000 – REVISED NOVEMBER 2008
over operating free-air temperature (unless otherwise noted)
(1)
UNIT
Supply voltage, (AVDD, DVDD to GND)
7 V
Reference input voltage range
- 0.3 V to AVDD + 0.3
Digital input voltage range
- 0.3 V to DVDD + 0.3
Operating free-air temperature range, TA
-40°C to 85°C
Storage temperature range, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1)
Stresses beyond those listed under absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN
TYP
MAX
UNIT
5-V operation
4.5
5
5.5
V
Supply voltage, AVDD, DVDD
3-V operation
2.7
3
3.3
V
DVDD = 2.7 V
2
High-level digital input, VIH
V
DVDD = 5.5 V
2.4
DVDD = 2.7 V
0.6
Low-level digital input, VIL
V
DVDD = 5.5 V
1.0
AVDD = 5 V, See
(1)
GND
2.048
AVDD
Reference voltage, Vref
V
AVDD = 3 V, See
(1)
GND
1.024
AVDD
Analog output load resistance, RL
2
k
Analog output load capacitance, CL
100
pF
Clock frequency, fCLK
30
MHz
Operating free-air temperature, TA
-40
85
°C
(1)
Reference input voltages greater than AVDD/2 causes saturation for large DAC codes.
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Fast
16
21
No load, All inputs = DVDD or GND,
IDD
Power supply current
mA
Vref = 2.048 V, See
(1)
Slow
6
8
Power-down supply
0.1
A
current
POR
Power on threshold
2
V
Power supply rejection
PSRR
Full scale, See (2)
-50
dB
ratio
(1)
IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7 V and VIL > 0.7 V, supply current increases.
(2)
Power supply rejection ratio at full scale is measured by varying AVDD and is given by: PSRR = 20 log [(EG(AVDDmax) -
EG(AVDDmin))/VDDmax]
Copyright 2000–2008, Texas Instruments Incorporated
3
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