參數(shù)資料
      

      


      


      
型號(hào)：
TLV5631IDWR

      

      
廠商：
TEXAS INSTRUMENTS INC

      

      
元件分類(lèi)：
DAC

      

      
英文描述：
SERIAL INPUT LOADING, 3 us SETTLING TIME, 10-BIT DAC, PDSO20

      

      
封裝：
GREEN, PLASTIC, SOIC-20

      

      
文件頁(yè)數(shù)：
17/21頁(yè)

      

      
文件大?。?/td>
511K

      

      
代理商：
TLV5631IDWR


      

      

      

	
      
    
    

    
      
	
      DIGITAL INPUT TIMING REQUIREMENTS
      www.ti.com .................................................................................................................................................... SLAS269F – MAY 2000 – REVISED NOVEMBER 2008
      ELECTRICAL CHARACTERISTICS (continued)
      over recommended operating conditions (unless otherwise noted)
      PARAMETER
      TEST CONDITIONS
      MIN
      TYP
      MAX
      UNIT
      DIGITAL OUTPUT
      High-level digital output
      RL = 10 k
      VOH
      2.6
      V
      voltage
      Low-level digital output
      RL = 10 k
      VOL
      0.4
      V
      voltage
      Output voltage rise time RL = 10 k, CL = 20 pF, Includes propagation delay
      5
      10
      ns
      ANALOG OUTPUT DYNAMIC PERFORMANCE
      Fast
      1
      3
      Output settling time, full
      ts(FS)
      RL = 10 k, CL = 100 pF, See
      (5)
      s
      scale
      Slow
      3
      7
      Fast
      0.5
      1
      Output settling time,
      ts(CC)
      RL = 10 k, CL = 100 pF, See
      (6)
      s
      code to code
      Slow
      1
      2
      Fast
      4
      10
      SR
      Slew rate
      RL = 10 k, CL = 100 pF, See
      (7)
      V/
      s
      Slow
      1
      3
      Glitch energy
      See (8)
      4
      nV-s
      Channel crosstalk
      10 kHz sine, 4 VPP
      90
      dB
      (5)
      Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of
      0x080 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.
      (6)
      Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one
      count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.
      (7)
      Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
      (8)
      Code transition: TLV5630 - 0x7FF to 0x800, TLV5631 - 0x7FCto 0x800, TLV5632 - 0x7F0 to 0x800.
      PARAMETER
      MIN
      TYP
      MAX
      UNIT
      tsu(FS-CK)
      Setup time, FS low before next negative SCLK edge
      8
      ns
      Setup time, 16th negative edge after FS low on which bit D0 is sampled before rising edge
      tsu(C16-FS)
      10
      ns
      of FS.
      C mode only
      tsu(FS-C17)
      C mode, setup time, FS high before 17th negative edge of SCLK.
      10
      ns
      tsu(CK-FS)
      DSP mode, setup time, SLCK low before FS low.
      5
      ns
      twL(LDAC)
      LDAC duration low
      10
      ns
      twH
      SCLK pulse duration high
      16
      ns
      twL
      SCLK pulse duration low
      16
      ns
      tsu(FS-CK)
      Setup time, FS low before first negative SCLK edge
      8
      ns
      tsu(D)
      Setup time, data ready before SCLK falling edge
      8
      ns
      th(D)
      Hold time, data held valid after SCLK falling edge
      5
      ns
      twH(FS)
      FS duration high
      10
      ns
      twL(FS)
      FS duration low
      10
      ns
      See AC
      ts
      Settling time
      specs
      Copyright  2000–2008, Texas Instruments Incorporated
      5
      Product Folder Link(s): TLV5630 TLV5631 TLV5632
      
    
      
    
    
      


      


      

      相關(guān)PDF資料
      		

      PDF描述
      		

      
      

      
TLV5631IDWRG4
SERIAL INPUT LOADING, 3 us SETTLING TIME, 10-BIT DAC, PDSO20

      

      
TLV5632IDWR
SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO20

      

      
TLV5632IDW
SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO20

      

      
TLV5630IPWG4
SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20

      

      
TLV5630IPWRG4
SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20

      

      

      

      


      


      

      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
TLV5631IDWRG4
功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7V to 5.5V 10-Bit 8-Ch Ser W/Int Ref RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube

      

      
TLV5631IPW
功能描述:數(shù)模轉(zhuǎn)換器- DAC 10bit 8Chl DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube

      

      
TLV5631IPWG4
功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7V to 5.5V 10-Bit 8-Ch Ser W/Int Ref RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube

      

      
TLV5631IPWR
功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7V to 5.5V 10-Bit 8-Ch Ser W/Int Ref RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube

      

      
TLV5631IPWRG4
功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7V to 5.5V 10-Bit 8-Ch Ser W/Int Ref RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube

      

      
    
    
    
	
      	
    
    
     
     
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