參數(shù)資料
型號: TLV5630IPWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁數(shù): 5/21頁
文件大?。?/td> 511K
代理商: TLV5630IPWG4
REFERENCE
TLV56xx
V(REF)
Pin 16
10 F
m
100pF
REF
BUFFERED AMPLIFIER
www.ti.com .................................................................................................................................................... SLAS269F – MAY 2000 – REVISED NOVEMBER 2008
The DAC reference can be sourced internally or externally by programming bits D2 (R1) and D1 (R0) of the
CTRL0 register (address = 08h). If an external source of reference is applied to the REF pin, the device must be
configured to accept the external reference source by setting R1 and R0 to 00 or 01. If R1 and R0 is set to select
for internal reference, a voltage of 1.024 V (if R1 and R0 = 10) or 2.048 V (if R1 and R0 = 11) is available. The
internal reference can source up to 1 mA, therefore. it can be used as an external system reference. A
decoupling capacitor must be connected to the REF pin if internal reference is selected to ensure output stability.
A 1
F to 10 F capacitor in parallel to a 100 pF capacitor should be sufficient, see Figure 13.
Figure 13. Reference Pin Decoupling Connection
The DAC outputs are buffered by an amplifier with a gain of two, which are configurable as Class A (fast mode)
or Class AB (slow or low-power mode). The output buffers have near rail-to-rail output with short-circuit
protection, and can reliably drive a 2-k
load with a 100-pF load capacitance.
Copyright 2000–2008, Texas Instruments Incorporated
13
Product Folder Link(s): TLV5630 TLV5631 TLV5632
相關(guān)PDF資料
PDF描述
TLV5630IPWRG4 SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5631IPWRG4 SERIAL INPUT LOADING, 3 us SETTLING TIME, 10-BIT DAC, PDSO20
TLV5630IDWG4 SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5633CDWRG4 PARALLEL, WORD INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO20
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