參數(shù)資料
型號(hào)： TLV5627I
廠商： Texas Instruments, Inc.
英文描述： 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
中文描述： 2.7 V至5.5 V的8位4通道數(shù)字到模擬與電源降壓轉(zhuǎn)換器
文件頁(yè)數(shù)： 6/19頁(yè)
文件大小： 258K
代理商： TLV5627I
TLV5627C, TLV5627I
2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS232 – JUNE1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR
Output slew rate
CL = 100 pF, RL = 10 k
,
VO = 10% to 90%,
Vref = 2.048 V, 1024 V
To
±
0.1 LSB, CL
RL = 10 k
, See Notes 12 and 14
Fast
5
V/
μ
s
Slow
1
V/
μ
s
ts
Output settling time
Fast
2.5
4
μ
s
,
Slow
8.5
18
t( )
ts(c)
Output settling time code to code
Output settling time, code to code
To
±
0.1 LSB, CL
RL = 10 k
, See Notes 13 and 14
Code transition from 7F0 to 800
Fast
1
μ
s
,
Slow
2
Glitch energy
10
nV-sec
SNR
Signal-to-noise ratio
Sinewave generated by DAC,
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
fs = 400 KSPS, fOUT = 1.1 kHz sinewave,
CL = 100 pF, RL = 10 k
, BW = 20 kHz
57
S/(N+D)
THD
Signal to noise + distortion
Total harmonic distortion
49
–50
dB
SFDR
NOTES: 12. Settling time is the time for the output signal to remain within
±
0.1 LSB of the final measured value for a digital input code change
of 0x020 to 0xFF0 or 0xFF0 to 0x020.
13. Settling time is the time for the output signal to remain within
±
0.1 LSB of the final measured value for a digital input code change
of one count.
14. Limits are ensured by design and characterization, but are not production tested.
Spurious free dynamic range
60
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CS–FS)
tsu(FS–CK)
Setup time, CS low before FS
↓
Setup time, FS low before first negative SCLK edge
10
ns
8
ns
tsu(C16–FS)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
10
ns
tsu(C16–CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
10
ns
twH
twL
tsu(D)
th(D)
twH(FS)
Pulse duration, SCLK high
25
ns
Pulse duration, SCLK low
25
ns
Setup time, data ready before SCLK falling edge
8
ns
Hold time, data held valid after SCLK falling edge
5
ns
Pulse duration, FS high
20
ns
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