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參數(shù)資料
| 型號(hào)： | TLV5627C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN |
| 中文描述： | 2.7 V至5.5 V的8位4通道數(shù)字到模擬與電源降壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 258K |
| 代理商： | TLV5627C |
TLV5627C, TLV5627I
2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS232 – JUNE1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Voltage output
RL = 10 k
0
AVDD–0.1
V
Output load regulation accuracy
RL = 2 k
vs 10 k
0.1
0.25
% of FS
voltage
reference input (REFINAB, REFINCD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
RI
CI
Input voltage range
See Note 8
0
AVDD–1.5
V
Input resistance
10
M
pF
Input capacitance
5
Reference feed through
REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 9)
–75
dB
Reference input bandwidth
REFIN = 0 2 V
REFIN = 0.2 Vpp + 1.024 V dc
+ 1 024 V dc
Slow
Fast
0.5
MHz
1
NOTES:
8. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
9. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD)
input = 1.024 Vdc + 1 Vpp at 1 kHz.
digital inputs (D0–D11, CS, WEB, LDAC, PD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
μ
A
pF
IIH
IIL
CI
High-level digital input current
VI = DVDD
VI = 0 V
±
1
±
1
Low-level digital input current
Input capacitance
3
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
1.4
MAX
2.2
UNIT
5 V supply No load Clock running
5-V supply, No load, Clock running
Slow
mA
IDD
Power supply current
Fast
3.5
5.5
3 V supply No load Clock running
3-V supply, No load, Clock running
Slow
1
1.5
mA
Fast
3
4.5
Power down supply current, See Figure 12
1
μ
A
PSRR
Power supply rejection ratio
Zero scale gain
Gain
See Notes 10 and 11
–68
–68
dB
10. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5
±
0.5 V and 3
±
0.5 V dc, and measuring the
proportion of this signal imposed on the zero-code output voltage.
11. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5
±
0.5 V and 3
±
0.5 V dc and measuring the proportion
of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
相關(guān)PDF資料 |
PDF描述 |
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| TLV5627I | 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN |
| TM-4-DC1 | CONNECTOR ACCESSORY |
| TM-6-DC | CONNECTOR ACCESSORY |
| TM-6-DC1 | CONNECTOR ACCESSORY |
| TM-8-DC | CONNECTOR ACCESSORY |
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