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參數(shù)資料
| 型號(hào)： | TLV5623IDGKG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 9 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MSOP-8 |
| 文件頁(yè)數(shù)： | 4/23頁(yè) |
| 文件大小： | 578K |
| 代理商： | TLV5623IDGKG4 |
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TLV5623C, TLV5623I
2.7V TO 5.5V LOW POWER 8BIT DIGITALTOANALOG
CONVERTERS WITH POWER DOWN
SLAS231B JUNE 1999 REVISED APRIL 2004
12
WWW.TI.COM
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5623 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
FSX
DX
CLKX
TLV5623
FS
DIN
SCLK
CS
SPI
SS
MOSI
SCLK
TLV5623
FS
DIN
SCLK
CS
Microwire
I/O
SO
SK
TLV5623
FS
DIN
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5623. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
SCLKmax +
1
t
wH(min) )
t
wL(min)
+ 20 MHz
The maximum update rate is:
f
UPDATEmax +
1
16 t
wH(min) )
t
wL(min)
+ 1.25 MHz
The maximum update rate is a theoretical value for the serial interface, since the settling time of the TLV5623
has to be considered also.
data format
The 16-bit data word for the TLV5623 consists of two parts:
D Control bits
(D15 . . . D12)
D New DAC value
(D11 ...D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
SPD
PWR
X
New DAC value (8 bits)
0
X: don’t care
SPD: Speed control bit.
1
→ fast mode
0
→ slow mode
PWR: Power control bit.
1
→ power down
0
→ normal operation
In power-down mode, all amplifiers within the TLV5623 are disabled.
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