參數(shù)資料
型號(hào)： TLV5621EDG4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 75 us SETTLING TIME, 8-BIT DAC, PDSO14
封裝： GREEN, PLASTIC, SOIC-14
文件頁(yè)數(shù)： 3/19頁(yè)
文件大?。?/td> 321K
代理商： TLV5621EDG4
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
VDD = 3 V to 3.6 V, Vref = 1.25 V, GND = 0 V, RL = 10 k, CL = 100 pF, × 1 gain output range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOmax
Maximum full-scale output
voltage
Vref = 1.5 V, open circuit output, × 2 gain
VDD – 100
2
mV
IIH(digital)
High-level digital input current
VI = VDD
±10
A
IIL(digital)
Low-level digital input current
VI = 0 V
±10
A
Output sink current, DACA
DAC code 0
5
A
IO(sink)
Output sink current, DACB,
DACC, DACD
DAC code 0
20
A
IO(source)
Output source current
Each DAC output,
DAC code 255
1
mA
Ci
Input capacitance
15
pF
Ci
Reference input capacitance
A, B, C, D inputs
15
pF
IDD
Supply current
VDD = 3.6 V
1
1.5
mA
IDD
Supply current
VDD = 5 V
1
1.5
mA
IDD(active)
Supply current, one low power
DAC active
VDD = 3.6 V, See Note 4
150
250
A
IDD(shutdown)
Supply current, all DACs shut
down
VDD = 3.6 V, See Note 4
50
100
A
Iref
Reference input current
A, B, C, D inputs
±10
A
EL
Integral linearity error
Vref = 1.25 V,
× 2 gain, See Notes 5 and 13
±1
LSB
ED
Differential linearity error
Vref = 1.25 V,
× 2 gain, See Notes 6 and 13
±0.1
±0.9
LSB
EZS
Zero-scale error
Vref = 1.25 V,
× 2 gain, See Note 7
0
30
mV
Zero-scale error temperature
coefficient
Vref = 1.25 V,
× 2 gain, See Note 8
10
V/°C
Zero-scale error supply rejection
2
mV/V
EFS
Full-scale error
Vref = 1.25 V,
× 2 gain, See Note 9
±60
mV
Full-scale error temperature
coefficient
Vref = 1.25 V,
× 2 gain, See Note 10
±25
V/°C
Full-scale error supply rejection
2
mV/V
PSRR
Power-supply sensitivity
See Notes 11 and 12
0.5
mV/V
Feedback resistor network
resistance
168
k
NOTES:
4. This is measured with no load (open circuit output), Vref = 1.25 V, range = × 2.
5. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
6. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
7. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
8. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) – ZSE(Tmin)]/Vref × 106/(Tmax – Tmin).
9. Full-scale error is the deviation from the ideal full-scale output (Vref – 1 LSB) with an output load of 10 k.
10. Full-scale temperature coefficient is given by: FSETC = [FSE(Tmax) – FSE (Tmin)]/Vref × 106/(Tmax – Tmin).
11. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect
of this signal on the zero-code output voltage.
12. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD voltage from 3 V to 3.6 V dc and measuring the effect of
this signal on the full-scale output voltage.
13. Linearity is only specified for DAC codes 1 through 255.
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