參數(shù)資料
型號(hào)： TLV5619QDWR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝： PLASTIC, SOIC-20
文件頁(yè)數(shù)： 18/23頁(yè)
文件大?。?/td> 478K
代理商： TLV5619QDWR
www.ti.com
ELECTRICAL CHARACTERISTICS
TLV5619
SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004
over recommended operating free-air temperature range, sdupply voltages, and reference voltages (unless otherwise noted)
STATIC DAC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
Vref(REFIN) = 2.048 V at 5 V, 1.024 V at 3 V
12
bits
Vref(REFIN) = 2.048 V at 5 V,
Integral nonlinearity (INL)
See (1)
±1.5
±4
LSB
1.024 V at 3 V,
Vref(REFIN) = 2.048 V at 5 V,
Differential nonlinearity (DNL)
See (2)
±0.4
±1
LSB
1.024 V at 3 V,
Vref(REFIN) = 2.048 V at 5 V,
EZS
Zero-scale error (offset error at zero scale)
See (3)
±3
±20
mV
1.024 V at 3 V,
Vref(REFIN) = 2.048 V at 5 V,
Zero-scale-error temperature coefficient
See (4)
3
ppm/
°C
1.024 V at 3 V,
Vref(REFIN) = 2.048 V at 5 V,
% of FS
EG
Gain error
See (5)
±0.25
±0.5
1.024 V at 3 V,
voltage
Vref(REFIN) = 2.048 V at 5 V,
Gain error temperature coefficient
See (6)
1
ppm/
°C
1.024 V at 3 V,
Zero scale
65
PSRR
Power-supply rejection ratio
See (7) and (8)
dB
Gain
65
(1)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from
the line between zero and full scale excluding the effects of zero code and full-scale errors.
(2)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)
as a change in the digital input code.
(3)
Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
(4)
Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref× 10
6/(T
max - Tmin).
(5)
Gain error is the deviation from the ideal output (2
× V
ref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error.
(6)
Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref× 10
6/(T
max - Tmin).
(7)
Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this
signal imposed on the zero-code output voltage.
(8)
Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.
OUTPUT SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Voltage output range
RL = 10 k
0
VDD-0.4
V
% of FS
Output load regulation accuracy
VO(OUT)= 4.096 V, 2.048 V
RL = 2 k
0.1
0.29
voltage
5-V Supply
100
VO(OUT) = 0 V, Full scale
IOSC(source)
Output short circuit source current
mA
code
3-V Supply
25
5-V Supply
10
IO(source)
Output source current
RL = 100
mA
3-V Supply
10
4
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