參數(shù)資料
型號: TLV5616C
廠商: Texas Instruments, Inc.
英文描述: 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
中文描述: 2.7 V至5.5 V低功耗12位數(shù)字至模擬與電源降壓轉(zhuǎn)換器
文件頁數(shù): 15/23頁
文件大小: 310K
代理商: TLV5616C
TLV5616C, TLV5616I
2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152B – DECEMBER 1997 – REVISED MARCH 1999
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
TLV5616 interfaced to MCS51
microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5616 to an MCS51
compatible microcontroller. The
serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent
on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide
the chip select and frame sync signals for the TLV5616.
SDIN
SCLK
CS
FS
OUT
REFIN
AGND
REF
RxD
TxD
P3.4
P3.5
MCS51
Controller
TLV5616
VDD
RLOAD
Figure 18. TLV5616 to MCS51
Controller Interface
software
The example program puts out a sine wave on the OUT pin.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine fetches
and writes the next sample to the DAC. The samples are stored in a lookup table, which describes one full period
of a sine wave.
The serial port of the controller is used in mode 0, which transmits 8 bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the
TLV5616. The CS and FS signals are provided in the required fashion through control of I/O port 3, which has
bit addressable outputs.
;***************************************************************************************
;* Title : Ramp generation with TLV5616 *
;* Version : 1.0 *
;* MCU : INTEL MCS51
*
;*
(1998) Texas Instruments Incorporated *
;***************************************************************************************
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Program function declaration
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
NAME
GENSINE
MAIN
ISR
SINTBL SEGMENT
VAR1
SEGMENT
STACK
SEGMENT
SEGMENT
SEGMENT
CODE
CODE
CODE
DATA
IDATA
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code start at address 0, jump to start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0
MCS is a registered trademark of Intel Corporation
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