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參數(shù)資料
| 型號： | TLV5613PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN |
| 中文描述： | 2.7 V至5.5 V 12位并行數(shù)字至模擬轉(zhuǎn)換器與電源向下 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 291K |
| 代理商： | TLV5613PW |
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174A – DECEMBER 1997 – REVISED JULY 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
reference input (REFIN)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vref
Ri
Ci
Input voltage reference
See Note 10
0
AVDD–1.5
V
Input resistance
10
M
pF
MHz
Input capacitance
5
Reference input bandwidth
Reference in ut bandwidth
REF = 0 2 Vpp+ 1 024 V dc
REF = 0.2 Vpp + 1.024 V dc
Fast mode
1.6
Slow mode
1
MHz
Reference feed through
REF = 1 Vpp at 1 kHz + 1.024 V dc,
See Note 10
–60
dB
NOTES: 10. Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
μ
A
pF
IIH
IIL
Ci
High-level digital input current
VI = DVDD
VI = 0 V
1
Low-level digital input current
–1
Input capacitance
8
operating characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
See Note 11
MIN
TYP
MAX
UNIT
t(FS)
ts(FS)
Output settling time full scale
Output settling time, full scale
RL = 10 k
,
CL = 100 pF,
Fast
1
3
μ
s
Slow
3.5
7
t(CC)
ts(CC)
Output settling time code to code
Output settling time, code-to-code
RL = 10 k
CL = 100 pF,
See Note 12
Fast
0.5
1.5
μ
s
,
Slow
1
2
SR
Slew rate
RL = 10 k
CL = 100 pF,
Code-to-code transition
See Note 13
Fast
8
V/
μ
s
,
Slow
1.5
Glitch energy
1
nV–s
S/N
Signal-to-noise
65
78
S/(N+D)
Signal-to-noise + distortion
fs = 480 KSPS, fout
RL = 10 k,
58
69
dB
THD
Total harmonic distortion
CL = 100 pF
,
–68
–60
Spurious free dynamic range
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0x3FF or 0x3FF to 0x020.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of one count. The max time applies to code changes near zero scale or full scale.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
60
72
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