參數(shù)資料
型號(hào)： TLV5606DGK
廠商： Texas Instruments, Inc.
英文描述： 2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
中文描述： 2.7 V至5.5 V低功耗10位數(shù)字至模擬與電源降壓轉(zhuǎn)換器
文件頁(yè)數(shù)： 4/22頁(yè)
文件大?。?/td> 298K
代理商： TLV5606DGK
TLV5606
2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS259 – DECEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
static DAC specifications R
L
= 10 k
, C
L
= 100 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
10
10
bits
INL
Integral nonlinearity
See Note 4
±
0.5
±
0.2
±
1.5
±
1
±
10
LSB
DNL
Differential nonlinearity
See Note 5
LSB
EZS
Zero-scale error (offset error at zero scale)
See Note 6
mV
Zero-scale-error temperature coefficient
See Note 7
10
ppm/
°
C
% of
FS
voltage
EG
Gain error
See Note 8
±
0.6
Gain-error temperature coefficient
4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(Tmax) – EZS(Tmin)]/Vref
×
106/(Tmax – Tmin).
8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k
excluding the effects of the zero-error.
9. Gain temperature coefficient is given by: EGTC = [EG(Tmax) – EG (Tmin)]/Vref
×
106/(Tmax – Tmin).
output specifications
See Note 9
10
ppm/
°
C
NOTES:
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Voltage output range
RL = 10 k
0
AVDD–0.1
V
Output load regulation accuracy
RL = 2 k
, vs 10 k
0.1
±
0.25
% of FS
voltage
reference input (REF)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
RI
CI
Input voltage range
0
VDD–1.5
V
Input resistance
10
M
pF
Input capacitance
5
Reference input bandwidth
REFIN = 0 2 V
REFIN = 0.2 Vpp + 1.024 V dc
+ 1 024 V dc
Slow
525
kHz
Fast
1.3
MHz
Reference feed through
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)
–75
dB
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
μ
A
pF
IIH
IIL
CI
High-level digital input current
VI = VDD
VI = 0 V
±
1
±
1
Low-level digital input current
Input capacitance
3
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