參數(shù)資料
型號(hào)： TLV5604D
廠商： Texas Instruments, Inc.
英文描述： 2.7-V TO 5.5-V 10-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
中文描述： 2.7 V至5.5 V的10位3毫秒翻兩番數(shù)字至模擬與電源降壓轉(zhuǎn)換器
文件頁(yè)數(shù)： 18/27頁(yè)
文件大?。?/td> 359K
代理商： TLV5604D
TLV5604
2.7-V TO 5.5-V 10-BIT 3-
μ
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
; Interrupt Service Routines
;–––––––––––––––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
int1
ret
; do nothing and return
int23
ret
; do nothing and return
timer_isr:
in
iosr_stat, IOSR ; store IOSR value into variable space
lacl
iosr_stat
; load acc with iosr status
and
#0FFFDh
; reset IO1 – LDAC low
sacl
temp
;
out
temp, IOSR ;
or
sacl
out
and
sacl
out
lacl
add
sacl
add
sacl
add
sacl
add
sacl
mar
#0002h
temp
temp, IOSR
#0FFFEh
temp
temp, IOSR
r_ptr
#sinevals
DACa_ptr
#08h
DACc_ptr
#08h
DACb_ptr
#08h
DACd_ptr
*,ar0
; set IO1 – LDAC high
;
;
; reset IO0 – CS low
;
;
; load rolling pointer to accumulator
; add pointer to table start
; to get a pointer for next DAC a sample
; add 8 to get to DAC C pointer
; add 8 to get to DAC B pointer
; add 8 to get to DAC D pointer
; set ar0 as current AR
; DAC A
lar
lacl
or
sacl
out
ar0, DACa_ptr; ar0 points to DAC a sample
*
; get DAC a sample into accumulator
#DACa_control; OR in DAC A control bits
temp
;
temp, SDTR
; send data
;–––––––––––––––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
; We must wait for transmission to complete before writing next word to the SDTR.
; TLV5604 interface does not allow the use of burst mode with the full packet rate, as
; we need a CLKX –ve edge to clock in last bit before FS goes high again, to allow SPI
; compatibility.
;–––––––––––––––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
rpt
#016h
; wait long enough for this configuration
nop
; of MCLK/CLKOUT1 rate
; DAC B
lar
lacl
or
sacl
out
rpt
nop
ar0, DACb_ptr; ar0 points to DAC a sample
*
; get DAC a sample into accumulator
#DACb_control; OR in DAC B control bits
temp
;
temp, SDTR
; send data
#016h
; wait long enough for this configuration
; of MCLK/CLKOUT1 rate
相關(guān)PDF資料
PDF描述
TLV5604PW 2.7-V TO 5.5-V 10-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5606D 2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5606DGK 2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5613DW 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TLV5613PW 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
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