參數(shù)資料
型號(hào): TLV5510INSR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24
封裝: PLASTIC, SOP-24
文件頁(yè)數(shù): 5/20頁(yè)
文件大?。?/td> 330K
代理商: TLV5510INSR
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
functional description
The TLV5510 is a semiflash ADC featuring two lower comparator blocks of four bits each.
As shown in Figure 19, input voltage VI(1) is sampled with the falling edge of CLK1 to the upper comparators
block and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1)
with the rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising
edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. According
to the above internal operation described, output data is delayed 2.5 clocks from the analog input voltage
sampling point.
Input voltage VI(2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, and
LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) is output with the rising
edge of CLK5.
VI(1)
VI(2)
VI(3)
VI(4)
CLK1
CLK2
CLK3
CLK4
S(1)
C(1)
S(2)
C(2)
S(3)
C(3)
S(4)
C(4)
S(1)
H(1)
C(1)
S(3)
H(3)
C(3)
H(0)
C(0)
S(2)
H(2)
C(2)
S(4)
H(4)
LD(– 2)
OUT(– 2)
OUT(–1)
OUT(0)
OUT(1)
ANALOG IN
(Sampling Points)
CLK (Clock)
Upper Comparators Block
Upper Data
Lower Reference Voltage
Lower Comparators Block (A)
Lower Data (A)
Lower Comparators Block (B)
Lower Data (B)
D1 – D8 (Data Output)
UD(0)
RV(0)
UD(1)
RV(1)
UD(2)
RV(2)
UD(3)
RV(3)
LD(– 1)
LD(0)
LD(1)
LD(2)
Figure 19. Internal Functional Timing Diagram
相關(guān)PDF資料
PDF描述
TLV5510IPW 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24
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