參數(shù)資料
型號： TLV320DAC32IRHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 40/69頁
文件大?。?/td> 1242K
代理商： TLV320DAC32IRHBR
www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008
Page 0 / Register 40:
High Power Output Stage Control Register (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D3–D2
R/W
00
LINER Bypass Path Control
00: LINER bypass is disabled
01: LINER bypass uses LINER
10: Reserved. Do not write this sequence to these register bits.
11: Reserved. Do not write this sequence to these register bits.
D1–D0
R/W
00
Output Volume Control Soft-Stepping
00: Output soft-stepping = one step per Fs
01: Output soft-stepping = one step per 2Fs
10: Output soft-stepping disabled
11: Reserved. Do not write this sequence to these register bits.
Page 0 / Register 41:
DAC Output Switching Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Left DAC Output Switching Control
00: Left DAC bypass disabled.
01: Reserved. Do not write to this bit.
10: Left DAC bypass enabled (Left DAC direct path enabled)
11: Reserved. Write only zero to this register bit.
D5–D4
R/W
00
Right DAC Output Switching Control
00: Right DAC bypass disabled.
01: Reserved. Do not write to this bit.
10: Right DAC bypass enabled (Right DAC direct path enabled)
11: Reserved. Write only zero to this register bit.
D3–D2
R/W
00
Reserved. Write only zeros to these bits.
D1–D0
R/W
00
DAC Digital Volume Control Functionality
00: Left and right DAC channels have independent volume controls
01: Left DAC volume follows the right channel control register
10: Right DAC volume follows the left channel control register
11: Left and right DAC channels have independent volume controls (same as 00)
Page 0 / Register 42:
Output Driver Pop Reduction Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
0000
Output Driver Power-On Delay Control
0000: Driver power-on time = 0-
sec
0001: Driver power-on time = 10-
sec
0010: Driver power-on time = 100-
sec
0011: Driver power-on time = 1-msec
0100: Driver power-on time = 10-msec
0101: Driver power-on time = 50-msec
0110: Driver power-on time = 100-msec
0111: Driver power-on time = 200-msec
1000: Driver power-on time = 400-msec
1001: Driver power-on time = 800-msec
1010: Driver power-on time = 2-sec
1011: Driver power-on time = 4-sec
1100–1111: Reserved. Do not write these sequences to these register bits.
D3-D2
R/W
00
Driver Ramp-up Step Timing Control
00: Driver ramp-up step time = 0-msec
01: Driver ramp-up step time = 1-msec
10: Driver ramp-up step time = 2-msec
11: Driver ramp-up step time = 4-msec
D1
R/W
0
Weak Output Common-mode Voltage Control
0:
Weakly driven output common-mode voltage is generated from bandgap reference
1:
Weakly driven output common-mode voltage is generated from resistor divider off the
AVDD_DAC supply
D0
R/W
0
Reserved. Write only zero to this register bit.
Copyright 2006–2008, Texas Instruments Incorporated
45
Product Folder Link(s): TLV320DAC32
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