SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ..................................................." />
參數(shù)資料
型號(hào)： TLV320AIC31IRHBT
廠商： Texas Instruments
文件頁數(shù)： 54/84頁
文件大?。?/td> 0K
描述： IC CODEC STEREO AUDIO 32-QFN
標(biāo)準(zhǔn)包裝： 1
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 標(biāo)準(zhǔn)包裝
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
其它名稱： 296-19422-6
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
Page 0 / Register 51:
HPLOUT Output Level Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
0000
HPLOUT Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
R/W
0
HPLOUT Mute
0: HPLOUT is muted
1: HPLOUT is not muted
D2
R/W
1
HPLOUT Power Down Drive Control
0: HPLOUT is weakly driven to a common-mode when powered down
1: HPLOUT is 3-stated with powered down
D1
R
1
HPLOUT Volume Control Status
0: Not all programmed gains to HPLOUT have been applied yet
1: All programmed gains to HPLOUT have been applied
D0
R/W
0
HPLOUT Power Control
0: HPLOUT is not fully powered up
1: HPLOUT is fully powered up
Page 0 / Register 52:
Reserved Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
0000000
Reserved. Write only '00000000' to this register.
Page 0 / Register 53:
PGA_L to HPLCOM Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPLCOM
1: PGA_L is routed to HPLCOM
D6-D0
R/W
0000000
PGA_L to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5.
Page 0 / Register 54:
DAC_L1 to HPLCOM Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLCOM
1: DAC_L1 is routed to HPLCOM
D6-D0
R/W
0000000
DAC_L1 to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5.
Page 0 / Register 55:
Reserved Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
0000000
Reserved. Write only '0000000' to this register.
58
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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參數(shù)描述
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