- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383957 > TLV320AIC3106IGQER (Texas Instruments, Inc.) LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY PDF資料下載
參數(shù)資料
| 型號： | TLV320AIC3106IGQER |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY |
| 中文描述： | 低功耗立體聲音頻編解碼器的便攜式音頻/電話 |
| 文件頁數(shù)： | 39/102頁 |
| 文件大?。?/td> | 1259K |
| 代理商： | TLV320AIC3106IGQER |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
www.ti.com
ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
In addition to the input bypass path described above, the TLV320AIC3106 also includes the ability to route the
ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the
output drivers. These bypass functions are described in more detail in the sections on output mixing and output
driver configurations.
INPUT IMPEDANCE AND VCM CONTROL
The TLV320AIC3106 includes several programmable settings to control analog input pins, particularly when they
are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a
3-state condition, such that the input impedance seen looking into the device is extremely high. Note, however,
that the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any
voltage is driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS,
these protection diodes will begin conducting current, resulting in an effective impedance that no longer appears
as a 3-state condition.
PASSIVE ANALOG BYPASS DURING POWERDOWN
Programming the TLV320AIC3106 to Passive Analog bypass occurs by configuring the output stage switches for
pass through. This is done by opening switches SW-L0, SW-L3, SW-R0, SW-R3 and closing either SW-L1 or
SW-L2 and SW-R1 or SW-R2. See
Figure 32
Passive Analog Bypass Mode Configuration. Programming this
mode is done by writing to Page 0, Register 108.
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input
voltage of the ADC PGA (which is determined by an internal bandgap voltage reference). This is useful to keep
the ac-coupling capacitors connected to analog inputs biased up at a normal DC level, thus avoiding the need
for them to charge up suddenly when the input is changed from being unselected to selected for connection to
an ADC PGA. This option is controlled in Page-0/Reg-20 and 23. The user should ensure this option is disabled
when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, since it
can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input pins on the TLV320AIC3106 should be ac-coupled to analog input sources, the
only exception to this generally being if an ADC is being used for DC voltage measurement. The ac-coupling
capacitor will cause a highpass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 20 k
with an input level control setting of
0-dB, and increasing to approximately 80-k
when the input level control is set at –12 dB. For example, using a
0.1
μ
F ac-coupling capacitor at an analog input will result in a highpass filter pole of 80 Hz when the 0 dB input
level control setting is selected.
Connecting MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0,
this action is done by writing a “1” to Page 0, Register 108, Bit D0. Connecting MIC2LP/LINE2LP input signal to
the LEFT_LOP pin is done by closing SW-L2 and opening SW-L0, this action is done by writing a “1” to Page 0,
Register 108, Bit D2. Connecting MIC1LM/LINE1LM input signal to the LEFT_LOM pin is done by closing
SW-L4 and opening SW-L3, this action is done by writing a “1” to Page 0, Register 108, Bit D1. Connecting
MIC2LM/LINE2LM input signal to the LEFT_LOM pin is done by closing SW-L5 and opening SW-L3, this action
is done by writing a “1” to Page 0, Register 108, Bit D3.
Connecting MIC1RP/LINE1RP input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening
SW-R0, this action is done by writing a “1” to Page 0, Register 108, Bit D4. Connecting MIC2RP/LINE2RP input
signal to the RIGHT_LOP pin is done by closing SW-R2 and opening SW-R0, this action is done by writing a “1”
to Page 0, Register 108, Bit D6. Connecting MIC1RM/LINE1RM input signal to the RIGHT_LOM pin is done by
closing SW-R4 and opening SW-R3, this action is done by writing a “1” to Page 0, Register 108, Bit D5.
Connecting MIC2RM/LINE2RM input signal to the RIGHT_LOM pin is done by closing SW-R5 and opening
SW-R3, this action is done by writing a “1” to Page 0, Register 108, Bit D7. A diagram of the passive analog
bypass mode configuration can be seen in
Figure 32
.
In general, connecting two switches to the same output pin should be avoided, as this error will short two input
signals together, and would like cause distortion of the signal as the two signal are in contention, and poor
frequency response would also likely occur.
39
Submit Documentation Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLV341_07 | LOW-VOLTAGE RAIL-TO-RAIL OUTPUT CMOS OPERATIONAL AMPLIFLERS WITH SHUTDOWN |
| TLV431ACDBV | LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS |
| TLV431ID | LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS |
| TLV431AIDBV | LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS |
| TLV431ASNT1 | MS/STANDARD CYLINDRICAL MIL-C-5015 SERIES 3102A SOLID SHELL BOX MOUNT RECEPTACLES, STRAIGHT BODY STYLE, SOLDER TERMINATION, 14S SHELL SIZE, 14S-6 INSERT ARRANGEMENT, RECEPTACLE GENDER, 6 CONTACTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC3106IRGZR | 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IRGZT | 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IZQE | 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IZQER | 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3107 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW-POWER STEREO CODEC WITH INTEGRATED MONO CLASS-D SPEAKER AMPLIFIER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。