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    參數(shù)資料
    

    


    


    
型號：
TLV320AIC29IRGZTG4

    

    
廠商：
TEXAS INSTRUMENTS INC

    

    
元件分類：
消費家電

    

    
英文描述：
SPECIALTY CONSUMER CIRCUIT, PQCC48

    

    
封裝：
7 X 7 MM, GREEN, PLASTIC, QFN-48

    

    
文件頁數(shù)：
20/87頁

    

    
文件大小：
1051K

    

    
代理商：
TLV320AIC29IRGZTG4


    

    

    

	
    
    
    

    
    
	
    TLV320AIC29
    SLAS494B  DECEMBER 2005  REVISED OCTOBER 2007
    www.ti.com
    27
    These coefficients implement a shelving filter with 0 dB gain from dc to approximately 150 Hz, at which point
    it rolls off to 3 dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz.
    The N and D coefficients are represented by 16bit twos complement numbers with values ranging from –32768
    to +32767. Frequency response plots are given in the Audio Codec Filter Frequency Responses section of this
    data sheet.
    Interpolation Filter
    The interpolation filter upsamples the output of the digital audio processing block by the required oversampling
    ratio. It provides a linear phase output with a group delay of 21/Fs.
    In addition, the digital interpolation filter provides enhanced image filtering to reduce signal images caused by
    the upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal
    images at multiples of 8 kHz, i.e., 8 kHz, 16 kHz, 24 kHz, etc. The images at 8 kHz and 16 kHz are below 20
    kHz and still audible to the listener, therefore, they must be filtered heavily to maintain a good quality output.
    The interpolation filter is designed to maintain at least 65 dB rejection of images that land below 7.455 Fs. In
    order to utilize the programmable interpolation capability, the Fsref should be programmed to a higher rate
    (restricted to be in the range of 39 kHz to 53 kHz when the PLL is in use), and the actual FS is set using the
    dividers in bits D5D3 of control register 00H/page 2. For example, if Fs = 8 kHz is required, then Fsref can be
    set to 48 kHz, and the DAC Fs set to Fsref/6. This ensures that all images of the 8-kHz data are sufficiently
    attenuated well beyond a 20-kHz audible frequency range. Passband ripple for all sample-rate cases (from 20
    Hz to 0.45 Fs) is +0.06 dB maximum.
    Delta-Sigma DAC
    The audio digital-to-analog converter incorporates a third order multi-bit delta-sigma modulator followed by an
    analog reconstruction filter. The DAC provides high-resolution, lownoise performance, using oversampling
    and noise shaping techniques. The analog reconstruction filter design consists of a 6 tap analog FIR filter
    followed by a continuous time RC filter. The analog FIR operates at 6.144 MHz (128x48 kHz, for Fsref of 48
    kHz) or at 5.6448 MHz (128x44.1 kHz, for Fsref of 44.1 kHz). The DAC analog performance may be degraded
    by excessive clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a
    minimum (less than 50ps).
    DAC Digital Volume Control
    The DAC has a digital volume control block, which implements programmable gain. The volume level can be
    varied from 0 dB to –63.5 dB in 0.5 dB steps, in addition to a mute bit, independently for each channel. The
    volume level of both channels can also be changed simultaneously by the master volume control. The gain is
    implemented with a softstepping algorithm, which only changes the actual volume by one step per input
    sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed to one
    step per two input samples through D1 of control register 04H/Page 2.
    Because of soft-stepping, the host does not know when the DAC has been completely muted. This may be
    important if the host wishes to mute the DAC before making a significant change, such as changing sample
    rates. In order to help with this situation, the part provides a flag back to the host via a read-only register bit
    (D2D3 of control register 04H/page 2) that alerts the host when the part has completed the soft-stepping, and
    the actual volume has reached the desired volume level. The soft-stepping feature can be disabled by
    programming D14=1 in register 1DH in Page 2. If soft-stepping is enabled, the MCLK signal should be kept
    applied to the device, until the DAC power-down flag is set. When this flag is set, the internal soft-stepping
    process and power down sequence is complete, and the MCLK can be stopped if desired.
    The AIC29 also includes functionality to detect when the user switches on or off the de-emphasis or digital audio
    processing functions, then (1) soft-mute the DAC volume control, (2) change the operation of the digital effects
    processing and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to
    instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC. The
    circuit begins operation at power-up with the volume control muted, then soft-steps it up to the desired volume
    level. At power-down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.
    
    
    
    
    
    


    


    

    相關PDF資料
    		

    PDF描述
    		

    
    

    
TLV320AIC29IRGZT
SPECIALTY CONSUMER CIRCUIT, PQCC48

    

    
TLV320AIC29IRGZ
SPECIALTY CONSUMER CIRCUIT, PQCC48

    

    
TLV320AIC3107IYZFR
2 CHANNEL, AUDIO AMPLIFIER, BGA42

    

    
TLV320AIC3107IYZFT
2 CHANNEL, AUDIO AMPLIFIER, BGA42

    

    
TLV320AIC3107IRSBT
2 CHANNEL, AUDIO AMPLIFIER, PQCC40

    

    

    

    


    


    

    相關代理商/技術參數(shù)
    		

    參數(shù)描述
    		

    
    

    
TLV320AIC3004IRHBR
 制造商:Texas Instruments 功能描述:TISTLV320AIC3004IRHBR LOW-POWER STEREO

    

    
TLV320AIC3007
 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW-POWER STEREO AUDIO CODEC WITH INTEGRATED MONO CLASS-D AMPLIFIER

    

    
TLV320AIC3007EVM-K
功能描述:音頻 IC 開發(fā)工具 TLV320AIC3007 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V

    

    
TLV320AIC3007IRSBR
功能描述:接口—CODEC Lo Pwr St CODEC w/ Integr Class-D Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel

    

    
TLV320AIC3007IRSBT
功能描述:接口—CODEC Lo Pwr St CODEC w/ Integr Class-D Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel

    

    
    
    
    
	
    	
    
    
     
     
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