參數(shù)資料
型號(hào): TLV320AIC26IRHBG4
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC
中文描述: 低功耗立體聲音頻編解碼器耳機(jī)/揚(yáng)聲器放大器和12位電池/溫度/輔助ADC
文件頁(yè)數(shù): 10/74頁(yè)
文件大?。?/td> 896K
代理商: TLV320AIC26IRHBG4
TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
18
D I2S MODE
In I2S mode, the MSB of the left channel is valid on the second rising edge of the BCLK after the falling edge of ADWS or
LRCK. Similarly the MSB of the right channel is valid on the second rising edge of the BCLK after the rising edge of
ADWS or LRCK.
BCLK
ADWS/
LRCK
DIN/
DOUT
n
n1
1
0
n
n1
1
0
LSB
MSB
n
1 clock before MSB
n2
2
n2
2
1/fs
Left Channel
Right Channel
Figure 16. Timing Diagram for I2S Mode
D DSP MODE
In DSP mode, the falling edge of ADWS or LRCK starts the data transfer with the left channel data first and immediately
followed by the right channel data. Each data bit is valid on the falling edge of BCLK.
BCLK
ADWS/
LRCK
DIN/
DOUT
n
n1
1
0
n
n1
1
0
LSB
MSB
n
n1
1
0
MSB
LSB
n2
2
n2
2
n2
MSB
LSB
1/fs
Left Channel
Right Channel
Figure 17. Timing Diagram for DSP Mode
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