- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄297500 > TLV320AIC26IRHB (Texas Instruments, Inc.) LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC PDF資料下載
參數(shù)資料
| 型號： | TLV320AIC26IRHB |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC |
| 中文描述： | 低功耗立體聲音頻編解碼器耳機(jī)/揚(yáng)聲器放大器和12位電池/溫度/輔助ADC |
| 文件頁數(shù)： | 13/74頁 |
| 文件大?。?/td> | 896K |
| 代理商： | TLV320AIC26IRHB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
20
D When PLL is enabled and D = 0, the following condition must be satisfied
80 MHz
v MCLK
K
P
v 110 MHz
2MHz
v MCLK
P
v 20 MHz
4
v J v 55
D When PLL is enabled and D ≠ 0, the following condition must be satisfied
80 MHz
v MCLK
K
P
v 110 MHz
10 MHz
v MCLK
P
v 20 MHz
4
v J v 11
Example 1:
For MCLK = 12 MHz and Fsref = 44.1 kHz
P = 1, K = 7.5264
J = 7, D = 5264
Example 2:
For MCLK = 12 MHz and Fsref = 48.0 kHz
P = 1, K = 8.192
J = 8, D = 1920
MONO AUDIO ADC
Analog Front End
The analog front end of the audio ADC consists of an analog MUX and a programmable gain amplifier (PGA). The MUX
can connect either the MICIN or AUX signal through the PGA to the ADC for audio recording. The ’AIC26 also has an option
of choosing both MICIN and AUX as a differential input pair. The ’AIC26 also includes a microphone bias circuit, which can
source up to 4.7-mA current and is programmable to a 2-V or 2.5-V level. The bias block is powered down when both the
ADC and analog mixer blocks are powered down.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for
analog antialiasing filtering are very relaxed. The ’AIC26 integrates a second order analog antialiasing filter with 20-dB
attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides sufficient antialiasing filtering without
requiring any external components.
The PGA allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with
an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC
output samples, depending on the register programming. This soft-stepping ensures that volume control changes occur
smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power down, the PGA
soft-steps the volume to mute before shutting down. A read-only flag (D0 control register 04H/Page2) is set whenever the
gain applied by PGA equals the desired value set by the register. The softstepping control can be disabled by
programming D15=1 in register 1DH of Page02. When soft-stepping is enabled, the MCLK signal to the device should not
be changed until the ADC power-down flag is set. When the flag is set, the internal soft-stepping process and power-down
sequence is complete, and the MCLK can be stopped if desired.
Delta-Sigma ADC
The analog-to-digital converter is a delta-sigma modulator with 128 times oversampling ratio. The ADC can support a
maximum output rate of 53 kHz.
Decimation Filter
The audio ADC includes an integrated digital decimation filter that removes high-frequency content and downsamples the
audio data from an initial sampling rate of 128 times Fs to the final output sampling rate of Fs. The decimation filter provides
a linear phase output response with a group delay of 17/Fs. The 3-dB bandwidth of the decimation filter extends to 0.45
Fs and scales with the sample rate (Fs)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLV320AIC29_07 | STWREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
| TLW-102-06-G-D-01 | 4 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER |
| TM16EN72LPU-40 | 16M X 72 EDO DRAM MODULE, 20 ns, DMA168 |
| TM16EN72LPU-60 | 16M X 72 EDO DRAM MODULE, 30 ns, DMA168 |
| TM3102 | 1200 MHz - 1700 MHz RF/MICROWAVE NARROW BAND LOW POWER AMPLIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC26IRHBG4 | 功能描述:接口—CODEC Octal Bus Trnscvr With 3-State Outputs RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC26IRHBR | 功能描述:接口—CODEC Lo-Pwr Stereo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC26IRHBRG4 | 功能描述:接口—CODEC Lo-Pwr Stereo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC27 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO CODEC |
| TLV320AIC27CPFB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。