參數(shù)資料
型號(hào)： TLV2711Y
廠商： Texas Instruments, Inc.
英文描述： Advanced LinCMOSE RAIL-TO-RAIL MICROPOWER SINGLE OPERATIONAL AMPLIFIERS
中文描述： 高級(jí)LinCMOSE軌至軌微功耗單運(yùn)算放大器
文件頁數(shù)： 25/28頁
文件大小： 551K
代理商： TLV2711Y
TLV2711, TLV2711Y
Advanced LinCMOS
RAIL-TO-RAIL
MICROPOWER SINGLE OPERATIONAL AMPLIFIERS
SLOS196 – AUGUST 1997
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads (continued)
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 52). To
use equation 1, UGBW must be approximated from Figure 52.
10 k
10 k
VDD–/GND
VDD+
Rnull
CL
VI
+
–
Figure 53. Series-Resistance Circuit
driving heavy dc loads
The TLV2711 is designed to provide better sinking and sourcing output currents than earlier CMOS rail-to-rail
output devices. This device is specified to sink 500
μ
A and source 250
μ
A at V
DD
= 3 V and V
DD
= 5 V at a
maximum quiescent I
DD
of 25
μ
A. This provides a greater than 90% power efficiency.
When driving heavy dc loads, such as 10 k
, the positive edge under slewing conditions can experience some
distortion. This condition can be seen in Figure 38. This condition is affected by three factors.
Where the load is referenced. When the load is referenced to either rail, this condition does not occur. The
distortion occurs only when the output signal swings through the point where the load is referenced.
Figure 39 illustrates two 10-k
load conditions. The first load condition shows the distortion seen for a 10-k
load tied to 2.5 V. The third load condition shows no distortion for a 10-k
load tied to 0 V.
Load resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 39
illustrates the difference seen on the output for a 10-k
load and a 100-k
load with both tied to 2.5 V.
Input signal edge rate. Faster input edge rates for a step input result in more distortion than with slower input
edge rates.
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