參數(shù)資料
型號(hào): TLV2548CPW
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): ADC
英文描述: 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁(yè)數(shù): 44/46頁(yè)
文件大?。?/td> 1078K
代理商: TLV2548CPW
TLV2544, TLV2548
2.7V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SLAS198E FEBRUARY 1999 REVISED JUNE 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control and timing (continued)
configuration
Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once
configured after first power up, the information is retained in the H/W or S/W power down state. When the device
is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stops
after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed.
Table 2. TLV2544/TLV2548 Configuration Register (CFR) Bit Definitions
BIT
DEFINITION
D11
Reference select
0: External
1: Internal (Tie REFM to analog ground if the Internal reference is selected.)
D10
Internal reference voltage select
0: Internal ref = 4 V
1: internal ref = 2 V
D9
Sample period select
0: Short sampling 12 SCLKs (1x sampling time)
1: Long sampling 24 SCLKs (2x sampling time)
D(8,7)
Conversion clock source select
00: Conversion clock = internal OSC
01: Conversion clock = SCLK
10: Conversion clock = SCLK/4
11: Conversion clock = SCLK/2
D(6,5)
Conversion mode select
00: Single shot mode [FIFO not used, D(1,0) has no effect.]
01: Repeat mode
10: Sweep mode
11: Repeat sweep mode
D(4,3)
TLV2548
TLV2544
D(4,3)
Sweep auto sequence select
00: 01234567
01: 02460246
10: 00224466
11: 02020202
Sweep auto sequence select
00: N/A
01: 01230123
10: 00112233
11: 01010101
D2
EOC/INT pin function select
0: Pin used as INT
1: Pin used as EOC
D(1,0)
FIFO trigger level (sweep sequence length)
00: Full (INT generated after FIFO level 7 filled)
01: 3/4 (INT generated after FIFO level 5 filled)
10: 1/2 (INT generated after FIFO level 3 filled)
11: 1/4 (INT generated after FIFO level 1 filled)
These bits only take effect in conversion modes 10 and 11.
sampling
The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion
commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).
相關(guān)PDF資料
PDF描述
TLV2548IDWR 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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