參數(shù)資料
      

      


      


      
型號(hào)：
TLV2541IDGKR

      

      
廠商：
TEXAS INSTRUMENTS INC

      

      
元件分類：
ADC

      

      
英文描述：
1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8

      

      
封裝：
GREEN, PLASTIC, MSOP-8

      

      
文件頁(yè)數(shù)：
27/31頁(yè)

      

      
文件大?。?/td>
778K

      

      
代理商：
TLV2541IDGKR


      

      

      

	
      
    
    

    
      
	
      TLV2541, TLV2542, TLV2545
      2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
      SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
      SLAS245E MARCH 2000  REVISED APRIL 2010
      5
      POST OFFICE BOX 655303
       DALLAS, TEXAS 75265
      POST OFFICE BOX 1443
       HOUSTON, TEXAS 772511443
      control and timing (continued)
      D Control via both CS and FS—The MSB is presented after the falling edge of CS. The falling edge of FS is
      the start of the sampling cycle. The MSB should be read on the first falling SCLK edge after FS is low. Output
      data changes on the rising edge of SCLK. This configuration is typically used for multiple devices connected
      to a TMS320 DSP.
      TLV2542/5
      All control is provided using CS (pin 1) on the TLV2542 and TLV2545. The cycle is started on the falling edge
      transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing
      is similar to the TLV2541, with control via CS only.
      TLV2542 channel MUX reset cycle
      The TLV2542 uses CS to reset the analog input multiplexer. A short active CS cycle (4 to 7 SCLKs) resets the
      MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as in the case for a complete
      conversion cycle (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel
      (see Figure 4 for timing). One dummy conversion cycle is recommended after power up before attempting to
      reset the MUX.
      sampling
      The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter
      has received a high-to-low CS transition (or a high-to-low FS transition for the TLV2541).
      conversion
      The TLV2541, TLV2542, and TLV2545 complete conversions in the following manner. The conversion is started
      after the 16th SCLK falling edge and takes 3.5 μs to complete. Enough time (for conversion) should be allowed
      before a rising CS or FS edge so that no conversion is terminated prematurely.
      TLV2542 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0
      via CS as described in the earlier section and in Figure 4. The input is sampled for 12 SCLKs, converted, and
      the result is presented on SDO during the next cycle. Care should also be taken to allow enough time between
      samples to avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is
      not complete.
      The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous
      cycle.
      timing diagrams/conversion cycles
      SCLK
      1
      2
      3
      4
      5
      6
      12
      13
      14
      15
      16
      1
      CS
      FS
      OD8
      OD7
      OD6
      OD5
      OD0
      SDO
      t(sample)
      tc
      t(powerdown)
      7
      OD10
      OD11
      OD9
      Figure 2. TLV2541 Timing: Control via CS (FS = 1)
      
    
      
    
    
      


      


      

      相關(guān)PDF資料
      		

      PDF描述
      		

      
      

      
TLV2542IDRG4
2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8

      

      
TLV2543CDBLE
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20

      

      
TLV2543IDWR
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20

      

      
TLV2543CN
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20

      

      
TLV2543CDW
11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20

      

      

      

      


      


      

      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
TLV2541IDGKRG4
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

      

      
TLV2541IDR
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

      

      
TLV2541IDRG4
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

      

      
TLV2542CDGK
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

      

      
TLV2542CDGKG4
功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

      

      
    
    
    
	
      	
    
    
     
     
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