參數(shù)資料
型號(hào)： TLV227X
廠商： Texas Instruments, Inc.
英文描述： FAMILY OF 2.7-V HIGH-SLEW-RATE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN
中文描述： 2.7家庭- V高，擺率軌到軌輸出運(yùn)算放大器具有關(guān)斷
文件頁數(shù)： 41/63頁
文件大?。?/td> 1135K
代理商： TLV227X
TLV277x, TLV277xA
FAMILY OF 2.7-V HIGH-SLEW-RATE RAIL-TO-RAIL OUTPUT
OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS209F
–
JANUARY 1998
–
REVISED MARCH 2001
41
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim
Parts
Release 8, the model generation
software used with Microsim
PSpice
. The Boyle macromodel (see Note 4) and subcircuit in Figure 64 are
generated using the TLV2772 typical electrical and operating characteristics at T
A
= 25
°
C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon,
“
Macromodeling of Integrated Circuit Operational Amplifiers
”
,
IEEE Journal
of Solid-State Circuits,
SC-9, 353 (1974).
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
OUT
+
–
+
–
53
+
–
+
–
+
–
+
–
+
–
+
–
VDD+
rp
2
IN
–
IN+
1
GND
rd1
11
j1
j2
10
rss
iss
3
12
rd2
ve
54
de
dp
vc
dc
4
C1
r2
6
9
egnd
vb
fb
C2
gcm
ga
vlim
8
5
ro1
ro2
hlim
90
dlp
91
dln
92
vln
vlp
99
7
css
* TLV2772 operational amplifier macromodel subcircuit
* created using Parts release 8.0 on 12/12/97 at 10:08
* Parts is a MicroSim product.
*
* connections: noninverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| | | | |
.subckt TLV2772
1 2 3 4 5
*
c1
11
12
c2
6
7
css
10
99
dc
5
53
de
54
5
dlp
90
91
dln
92
90
dp
4
3
egnd
99
0
fb
7
99
2.8868E-12
10.000E
–
12
2.6302E
–
12
dy
dy
dx
dx
dx
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
15.513E6
–
1E3 1E3 16E6
–
16E6
11 12 188.50E
–
6
10 99 9.4472E
–
9
ga
gcm
6
0
0
6
iss
hlim
j1
j2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
3
90
11
12
6
4
4
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
10
0
2
1
9
11
12
5
99
4
99
0
53
4
8
0
92
D(Is=800.00E
–
18)
D(Is=800.00E
–
18 Rs=1m Cjo=10p)
PJF(Is=2.2500E
–
12 Beta=244.20E
–
6
+ Vto=
–
.99765)
PJF(Is=1.7500E
–
12 Beta=244.20E
–
6
+ Vto=
–
1.002350)
dc
vlim 1K
10 jx1
10 jx2
100.00E3
5.3052E3
5.3052E3
17.140
17.140
4.5455E3
1.3746E6
dc 0
dc .82001
dc .82001
dc 0
dc 47
dc 47
145.50E
–
6
.model
jx2
.ends
*$
Figure 64. Boyle Macromodel and Subcircuit
PSpice
and
Parts
are trademarks of MicroSim Corporation.
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