參數(shù)資料
型號(hào)： TLV2254(中文)
廠商： Texas Instruments, Inc.
英文描述： Quad LINCMOS Rail-To-Rail Micropower OP AMP(四路滿電源幅度，低壓微功耗運(yùn)放)
中文描述： 四LINCMOS軌至軌微功率運(yùn)算放大器（四路滿電源幅度，低壓微功耗運(yùn)放）
文件頁(yè)數(shù)： 31/39頁(yè)
文件大小： 1029K
代理商： TLV2254(中文)
TLV2254, TLV2254A, TLV2254Y
Advanced LinCMOS
RAIL-TO-RAIL
VERY LOW POWER QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS140A – DECEMBER 1994 – REVISED MAY 1996
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads
The TLV2254 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 51
and Figure 52 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins
(R
null
= 0).
A smaller series resistor (R
null
) at the output of the device (see Figure 54) improves the gain and phase margins
when driving large capacitive loads. Figure 51 and Figure 52 show the effects of adding series resistances of
10
, 50
, 100
, 200
, and 500
. The addition of this series resistor has two effects: the first is that it adds
a zero to the transfer function and the second is that it reduces the frequency of the pole associated with the
output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation (1) can be used.
φ
m1
tan
–1
2
×
π
×
UGB
W
×
Rnull
×
CL
φ
m1
UGBW
R
null
improvement in phase margin
unity-gain bandwidth frequency
output series resistance
load capacitance
C
L
(1)
where :
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 53). To
use equation (1), UGBW must be approximated from Figure 53.
Using equation (1) alone overestimates the improvement in phase margin, as illustrated in Figure 54. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin.
Using Figure 55 with equation (1) enables the designer to choose the appropriate output series resistance to
optimize the design of circuits driving large capacitance loads.
50 k
50 k
VDD–/GND
VDD+
Rnull
CL
VI
+
–
Figure 55. Series-Resistance Circuit
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV2254AID 功能描述:運(yùn)算放大器 - 運(yùn)放 LiNCMOS R/R RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
TLV2254AIDG4 功能描述:運(yùn)算放大器 - 運(yùn)放 Quad Low-Voltage Rail-to-Rail RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
TLV2254AIDR 功能描述:運(yùn)算放大器 - 運(yùn)放 Quad Low-Voltage Rail-to-Rail RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
TLV2254AIDRG4 功能描述:運(yùn)算放大器 - 運(yùn)放 Quad Low-Voltage Rail-to-Rail RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
TLV2254AIN 功能描述:運(yùn)算放大器 - 運(yùn)放 LiNCMOS R/R RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
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