參數(shù)資料
型號(hào)： TLV1548(中文)
廠商： Texas Instruments, Inc.
英文描述： Low-Voltage 10-Bit ADC With Serial Control And 8 Analog Inputs(具串行控制和8通道模擬輸入，低壓10位ADC)
中文描述： 低電壓10位ADC，串行控制和8個(gè)模擬輸入（具串行控制和8通道模擬輸入，低壓10位ADC）的
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 938K
代理商： TLV1548(中文)
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CC
=V
ref+
=2. 7Vá5. 5V￡I/OCLKμê=2. 2MHzê±μ1¤×÷ì
D￡¨3y· áí óDμ÷￡
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
EL
ED
EO
EG
ET
Linearity error (see Note 6)
+
+
0.5
-
+
0.5
+
1
+
1
-
LSB
Differential linearity error
Offset error (see Note 7)
See Note 2
See Note 2
LSB
LSB
+
1.5
+
1
+
1.75
-
Gain error (see Note 7)
See Note 2
LSB
Total unadjusted error (see Note 8)
LSB
T
3
9)
DATA IN = 1011
DATA IN - 1100
512
Self-test output code (see able and Note
0
DATA IN = 1101
1023
tconv
Conversion time
Fast conversion speed
Slow conversion speed
See Figures 15
through 18
8
10
40
μ
s
μ
s
25
tc
Total cycle time (access,
sample conversion and
EOC to CS delay)
Fast conversion speed
See Figures 15
through 18 and
Notes 10, 11, 12
10.1
+ 10 I/O CLK
μ
s
Slow conversion speed
See Figures 15
through 18 and
Notes 10 and 12
25.1
+ 10 I/O CLK
tacq
Channel acquisition time (sample)
See Figures 15
through 18 and
Note 10
6
I/O
CLK
periods
tv
td1(FS)
td2(FS)
Valid time, DATA OUT remains valid after I/O CLK
Ο
Delay time, I/O CLK high to FS high
See Figure 11
50
ns
See Figure 13
5
30
50
ns
Delay time, I/O CLK high to FS low
See Figure 13
10
30
60
ns
td(EOC CS )
Delay time, EOC to CS low
See Figure 14
and Note 5
100
ns
td(I/O -CS)
Delay time, 10th I/O CLK low to CS low to abort
conversion (see Note 13)
See Figure 10
1.1
μ
s
td(I/O-DATA)
td(I/O-EOC)
tPZH, tPZL
Delay time, I/O CLK low to DATA OUT valid
See Figure 11
50
ns
Delay time, 10th I/O CLK to EOC low
See Figure 12
70
240
ns
μ
s
Enable time, CS low to DATA OUT valid (MSB driven)
See Figure 8
0.7
1.3
tPHZ, tPLZ
Disable time, CS high to DATA OUT invalid
(high impedance)
See Figure 8
70
150
ns
tf(EOC)
tr(bus)
tf(bus)
Fall time, EOC
See Figure 12
15
50
ns
Rise time, output data bus at 2.2 MHz I/O CLK
See Figure 11
50
250
ns
Fall time, output data bus at 2.2 MHz I/O CLK
See Figure 11
50
250
ns
-
-
-
-
-
+
ùóDμDíμê
T
A
=25
ê±μêyμ ￡
×￠êí￡o
2.
′óóú
REF
+
ùóμ1μ￡aêèμ1×aaè
1
￡¨
111111111111
￡D óú
REF
￡-
ùóμ1μêè
μ1×aaè
0
￡¨
000000000000
￡￡μ±ù×￡¨
V
REF+
￡-
V
REF
￡-
￡μíá
1V
ê±￡÷tè±￡31|ü￡μ
μìDêy2ùéó ￡
5.
óúùóD1¤×÷· ê ￡
6.
Dèó2 êú
A/D
×aòDDà× ±μ× ′óòá ￡
7.
áμó2 ê
000000000000
óáêèμ1μ×aê3 ￡úèó2 ê
111111111111
óúèêèμ
1μ×aê3 ￡
8.
×ü2éμ÷ó2 ￡¨
total unadjusted error
￡óéDè ￠áèoíúèó2 ×é3é ￡
9.
êèêyYoíê3′úóy±í ′ ￡
10. I/O CLK
üú
=1/
￡¨
I/O CLK
μê￡¨í
8
￡￡
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