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參數(shù)資料
| 型號： | TLP559 |
| 廠商： | Toshiba Corporation |
| 英文描述： | Digital Logic Ground Isolation Line Receiver Microprocessor System Interfaces Switching Power Supply Feedback Control Transistor Invertor |
| 中文描述： | 數(shù)字邏輯地面隔離線接收微處理器系統(tǒng)接口開關(guān)電源反饋控制晶體管變頻器 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 152K |
| 代理商： | TLP559 |
TLP559(IGM)
2002-05-27
3
COUPLED ELECTRICAL CHARACTERISTICS
(Ta = 25
℃
)
CHARACTERISTIC
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
I
F
= 10 mA, V
CC
= 4.5 V
V
O
= 0.4 V
25
35
75
Current Transfer Ratio
I
O
/ I
F
I
F
= 10 mA, V
CC
= 4.5 V
V
O
= 0.4 V, Ta =
25~100°C
15
―
―
%
Low Level Output Voltage
V
OL
I
F
= 16 mA, V
CC
= 4.5 V
I
O
= 2.4 mA
―
―
0.4
V
ISOLATION CHARACTERISTICS
(Ta = 25
℃
)
CHARACTERISTIC
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Capacitance Input to Output
CS
V = 0, f = 1 MHz
―
0.8
10
14
―
pF
Isolation Resistance
R
S
R.H.
≤
60%, V
S
= 500 V
5×10
10
―
AC , 1minute
2500
―
―
AC , 1second, in oil
―
5000
―
Vrms
Isolation Voltage
BV
S
DC , 1minute,in oil
―
5000
―
Vdc
SWITCHING CHARACTERISTICS
(Ta = 25
℃、
V
CC
= 15 V)
CHARACTERISTIC
SYMBOL
TEST
CIR-
CUIT
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
I
F
= 10 mA, R
L
= 20 k
0.1
0.45
0.8
I
F
= 10 mA, R
L
= 20 k
Ta = 0~85°C
0.1
0.45
0.9
Propagation Delay Time (H
→
L)
Propagation Delay Time (L
→
H)
t
pHL
t
pLH
I
F
= 10 mA, R
L
= 20 k
Ta =
25~100°C
0.1
0.45
1.0
μs
I
F
= 10 mA, R
L
= 20 k
―
0.15
0.7
I
F
= 10 mA, R
L
= 20 k
Ta = 0~85°C
―
0.25
0.8
Switching Time
Dispersion between ON
and OFF
|t
pLH
t
pHL
|
1
I
F
= 20 mA, R
L
= 20 k
Ta =
25~100°C
―
0.25
0.9
μs
Common Mode
Transient Immunity at
Logic High Output (Note 8)
CM
H
I
F
= 0 mA,
V
CM
= 1500 V
p
p,
R
L
= 20 k
I
F
=10 mA,
V
CM
= 1500 V
p
p,
R
L
= 20 k
10000 15000
―
V /μs
Common Mode
Transient Immunity at
Logic Low Output (Note 8)
CM
L
2
10000
15000
―
V /μs
(Note 8) CM
L
is the maximum rate of fall of the common mode voltage that can be
sustained with the output voltage in the logic low state(Vo<1V).
CM
H
is the maximum rate of rise of the common mode voltage that can be
sustained with the output voltage in the logic high state(Vo>4V).
(Note 9) Maximum electrostatic discharge voltage for any pins : 100V(C=200pF,R=0)
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