參數(shù)資料
型號: TLP558
廠商: Toshiba Corporation
英文描述: Isolated Bus Driver High Speed Line Receiver Microprocessor System Interfaces MOS FET Gate Driver Transistor Inverter
中文描述: 隔離總線驅(qū)動高速線接收微處理器系統(tǒng)接口場效應(yīng)晶體管柵極驅(qū)動晶體管逆變器
文件頁數(shù): 5/7頁
文件大?。?/td> 213K
代理商: TLP558
TLP558
2002-09-25
5
(Note 6) Duration of output short circuit time should not exceed 10ms.
(Note 7) The t
pLH
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.3V point on the leading edge of the output pulse. The t
pHL
propagation delay is measured from the 50%
point on the leading edge of the input pulse to the 1.3V point on the trailing edge of the output pulse.
(Note 8) C
ML
is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage
in the logic low state (V
O
> 0.8V).
C
MH
is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic state (V
O
> 2.0).
(Note 9) A ceramic capacitor (0.1μF) should be connected from pin 8 to pin 5 to stabilize the operation of the high
gain linear amplifier. Failure to provide the bypassing may impair the switching property. The total lead length
between capacitor and coupler should not exceed 1cm.
Test Circuit 1: t
pLH
, t
pHL
, t
r
And t
f
V
OL
1.3V
Input I
F
0mA
V
OH
t
pHL
I
F(ON)
Output V
O
t
r
t
f
90%
10%
50%
t
pLH
V
CC
Pulse generation
t
r
= t
f
= 5ns
V
O
= 5V
D1
D4
: 1S1588
D2
D3
D4
C
L
V
CC
GND
Monitor
C
L
is approximately 15pF which includes
probe and stray wiring capacitance.
D1
5V
6
4
3
1
5
7
I
F
Monitor
I
F
V
O
8
2
1
0
6
5
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