參數(shù)資料
型號(hào)： TLK4201EA
廠商： Texas Instruments, Inc.
英文描述： 4.25 Gbps Cable And PC Board Equalizer
中文描述： 4.25Gbps 電纜和 PC 主板均衡器
文件頁(yè)數(shù)： 11/17頁(yè)
文件大?。?/td> 727K
代理商： TLK4201EA
www.ti.com
DEVICE INFORMATION
GND
COC2
COC1
NC
1
2
3
4
VCC
DIN+
DIN
VCC
RGT PACKAGE
(TOP VIEW)
12
11
10
9
16
VCC
DOUT+
DOUT
OUTPOL
15
14
13
5
6
7
8
LOSDIS
DISABLE
LOS
GND
P0019-03
EP
TLK4201EA
SLLS719 – APRIL 2006
The TLK4201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN Package.
This quad package has a lead pitch of 0.5 mm. The pinout is shown in Figure 2.
Figure 2. Pinout of TLK4201EA
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
VCC
1, 4, 12
Supply
3.3V ± 10% supply voltage.
DIN+
2
Analog In
Noninverted data input. On-chip 100-
terminated to DIN–.
DIN–
3
Analog In
Inverted data input. On-chip 100-
terminated to DIN+.
LOS disable input. High level disables LOS circuitry and sets LOS pin to low level. Low level
LOSDIS
5
CMOS In
enables LOS function. This pin has approximately 825-k
internal electronic pulldown
resistor.
DISABLE
6
CMOS In
Disables CML output stage when set to high level. 400-k
on-chip pulldown resistor.
LOS
7
CMOS Out
High level indicates that the input signal amplitude is below the fixed threshold level.
GND
8, 16
Supply
Circuit ground
Output data signal polarity select with approximately 715-k
internal electronic pullup
resistor:
OUTPOL
9
CMOS In
Setting to high-level or leaving pin open selects normal polarity. Low-level selects inverted
polarity.
DOUT–
10
CML Out
Inverted data output. On-chip 50-
back-terminated to VCC.
DOUT+
11
CML Out
Noninverted data output. On-chip 50-
back-terminated to VCC.
NC
13
—
Not connected
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between
COC1
14
Analog
this pin and COC2 (pin 15).
To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between
COC2
15
Analog
this pin and COC1 (pin 14).
To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
EP
Exposed die pad (EP) must be grounded.
3
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