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參數(shù)資料
| 型號： | TLE6285 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | LIN-Transceiver LDO |
| 中文描述： | 林收發(fā)器穩(wěn)壓器 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大小： | 649K |
| 代理商： | TLE6285 |
Target Data
TLE 6285
Version 1.02
8
2002-05-15
very short, the
V
LD
level is not reached and no reset-signal is asserted. This feature
avoids resets at short negative spikes at the output voltage e.g. caused by load changes.
As soon as the output voltage is more positive than the reset threshold, the delay
capacitor is charged with constant current. When the voltage reaches
V
UD
the reset
output RO is set High again.
The reset threshold is either the internal defined
V
RT
voltage (typical 4.6 V) or can be
lowered by a voltage level at the R
Th
input down to 3.5 V. The reset delay time and the
reset reaction time are defined by the external capacitor
C
D
. The reset function is active
down to
V
I
= 1 V.
The device is capable to supply 150 mA. For protection at high input voltage above 25 V,
the output current is reduced (SOA protection).
2.5
Reset
The power on reset feature is necessary for a defined start of the microprocessor when
switching on the application. For the reset delay time after the output voltage of the
regulator is above the reset threshold, the reset signal is set High again. The reset delay
time is defined by the reset delay capacitor
C
D
at pin RD (refer to
figure 4 and 5
).
The under-voltage reset circuitry supervises the output voltage. In case
V
Q
decreases
below the reset threshold the reset output is set LOW after the reset reaction time. The
reset LOW signal is generated down to an output voltage
V
CC
to 1 V. Both the reset
reaction time and the reset delay time is defined by the capacitor value.
The power on reset delay time is defined by the charging time of an external delay
capacitor
C
D
.
C
D
= (
t
d
I
D
) /
V
With
C
D
reset delay capacitor
t
d
reset delay time
V
=
V
UD
,
typical 1.8 V for power up reset
V
=
V
UD
–
V
LD
typical 1.35 V for undervoltage reset
I
D
charge current typical 6.5 A
For a delay capacitor
C
D
=100 nF the typical power on reset delay time is 28 ms.
The reset reaction time
t
RR
is the time it takes the voltage regulator to set reset output
LOW after the output voltage has dropped below the reset threshold. It is typically 1 s
for delay capacitor of 100 nF. For other values for
C
D
the reaction time can be estimated
using the following equation:
t
RR
= 10 ns / nF
C
D
[1]
[2]
The reset output is an open collector output with a pull-up resistor of typical 20 k to Q.
An external pull-up can be added with a resistor value of at least 5.6 k .
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