參數(shù)資料
型號: TLE4941C
廠商: INFINEON TECHNOLOGIES AG
元件分類: 霍爾效應(yīng)傳感器
英文描述: Differential Two-Wire Hall Effect Sensor IC
中文描述: 差分兩線霍爾效應(yīng)傳感器IC
文件頁數(shù): 2/11頁
文件大?。?/td> 853K
代理商: TLE4941C
TLE4941, TLE4941C
TLE4941 - TLE 4941C Data Sheet
Febrary 2002
2
Functional Description
The differential hall sensor IC detects the motion of ferromagnetic and permanent
magnet structures by measuring the differential flux density of the magnetic field. To
detect the motion of ferromagnetic objects the magnetic field must be provided by a
back biasing permanent magnet. Either south or north pole of the magnet can be
attached to the rear unmarked side of the IC package.
Magnetic offsets of up to +/- 20mT and device offsets are cancelled by a self-
calibration algorithm. Only a few transitions are necessary for self-calibration. After
the initial calibration sequence switching occurs when the input signal is crossing the
arithmetic mean of its max and min value. (E.g. zero-crossing for sinusoidal signals)
The ON and OFF state of the IC are indicated by
High
and
Low
current
consumption.
Circuit Description
The circuit is supplied internally by a 3V voltage regulator. An on-chip oscillator
serves as clock generator for the digital part of the circuit.
TLE4941 signal path is comprised of a pair of hall probes, spaced at 2.5mm, a
differential amplifier including a noise-limiting low-pass filter and a comparator
feeding a switched current output stage. In addition an offset cancellation feedback
loop is provided by a signal-tracking A/D converter, a digital signal processor (DSP)
and an offset cancellation D/A converter.
During the startup phase (un-calibrated mode) the output is disabled (I=I
Low
).
The differential input signal is digitized in the speed A/D converter and fed into the
DSP. The minimum and maximum values of the input signal are extracted and their
corresponding arithmetic mean value is calculated. The offset of this mean value is
determined and fed into the offset cancellation DAC.
After successful correction of the offset, the output switching is enabled
.
In running mode (calibrated mode) the offset correction algorithm of the DSP is
switched into a low-jitter mode, avoiding oscillation of the offset DAC LSB. Switching
occurs at zero-crossing. It is only affected by the (small) remaining offset of the
comparator and by the remaining propagation delay time of the signal path, mainly
determined by the noise-limiting filter. Signals below a defined threshold
B
Limit
are
not detected to avoid unwanted parasitic switching.
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