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參數(shù)資料
| 型號： | TLE 6272 |
| 廠商： | SIEMENS AG |
| 英文描述： | CAN-LDO-ASIC(高速控制區(qū)域網(wǎng)絡接受器) |
| 中文描述： | 的CAN - LDO穩(wěn)壓器，專用集成電路（高速控制區(qū)域網(wǎng)絡接受器） |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 160K |
| 代理商： | TLE 6272 |
Target Data
TLE 6272
4
version: 1.01 date: 12.05.00
2
Application Information
The TLE 6272 is a dual chip IC that offers features of the CAN-transceiver TLE 6250 and
the voltage regulator TLE 4299 in one package.
The voltage regulator of the TLE 6272 is a PNP based very low drop linear voltage
regulator. It regulates the output voltage V
CC
= 5V at an input voltage range of
5.5V
≤
V
S
≤
45V. The control circuirtry protects the device against damages like
overcurrent and overtemperature.
The internal control circuit achieves a 5V output voltage with a tolerance of ± 2%.
The device includes a power-on reset and an under-voltage reset function with
adjustable reset delay time. Further there is implemented a separate enable / inhibit
function for both, the voltage regulator (including reset circuitry) and the CAN-
transceiver. By this the CAN-transceiver circuitry can be switched off to reduce the
power consumption while the voltage regulator still supplies other loads. When the
voltage regulator is disabled via the ENVR input also the CAN-transceiver is
automatically switched off due to the missing supply voltage via V
CC
.
The reset logic compares the output voltage V
CC
to an internal threshold. If the output
voltage drops below this level, the external reset delay capacitor C
D
is discharged.
When V
D
is lower than V
st
, the output reset is switched Low . If the output voltage drop
is very short, the V
st
level is not reached and no reset-signal is asserted. This feature
avoids resets at short negative spikes at the output voltage e. g. caused by load
changes. Please see figure 3, reset timing diagram.
As soon as the output voltage is more positive than the reset threshold, the delay
capacitor is charged with constant current. When the voltage reaches V
DU
the reset
output RO is set High again. (Reset-hysteresis)
The reset threshold V
RT
is internally defined (typical 4.65V). The reset delay time is
defined by the external capacitor C
D
that is charged by a constant current I
d
up to a
certain threshold V
dt
during power on phase. Please see figure 3, reset timing diagram.
The reset function is active down to V
cc
= 1V.
When the INHT is low while V
CC
is present, the CAN-transceiver circuitry is in the normal
operation mode. Then messages can be transmitted or received respectively via the
RxD and TxD pin. The CAN stand-by mode is a low power mode that disables both, the
receiver as well as the transmitter within the CAN-transceiver.
A message sent by the microcontroller to the TxD input is transformed to a differential
mode signal and sent to other CAN nodes via the CANH and CANL output. Differential
mode data on the bus lines is reported to the microcontroller via the RxD ouput.
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