參數(shù)資料
型號(hào): TLE 6263
廠商: SIEMENS AG
英文描述: CAN-LDO-ASIC(控制區(qū)域網(wǎng)絡(luò)低壓差用于汽車電路的專用集成電路)
中文描述: 的CAN - LDO穩(wěn)壓器,專用集成電路(控制區(qū)域網(wǎng)絡(luò)低壓差用于汽車電路的專用集成電路)
文件頁(yè)數(shù): 3/37頁(yè)
文件大?。?/td> 839K
代理商: TLE 6263
confidential
Preliminary Data
TLE 6263
3
version: 2.00 date: 19.12.00
1.3
Pin No.
1
2
3
4
Pin Definitions and Functions
Symbol
Function
TxD
Transmit data input;
integrated pull up
RxD
Receive data output;
RO
Reset output
; open drain output, integrated pull up, active low
WK2
Wake-Up input 2;
for detection of external wake-up events, level
sensitive, in sleep mode monitored by cyclic sense feature when
selected
WK1
Wake-Up input 1;
for detection of external wake-up events, edge
sensitive, in sleep mode monitored by cyclic sense feature when
selected
6, 7, 8, 9,
20, 21,
22, 23
10
DO
SPI data output
; this tri-state output transfers diagnosis data to
the control device; the output will remain 3-stated unless the
device is selected by a low on Chip-Select-Not (CSN); see
table 4, 5, 6
for Diagnosis protocol
11
CLK
SPI clock input
; clocks the shiftregister; CLK has an internal
active pull down and requires CMOS logic level inputs
12
CSN
SPI chip select not input
; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low; CSN
input should only be transitioned when CLK is low; CSN has an
internal active pull up and requires CMOS logic level inputs
13
DI
SPI data input
; receives serial data from the control device;
serial data transmitted to DI is a 8 bit control word with the Least
Significant Bit (LSB) being transferred first: the input has an
active pull down and requires CMOS logic level inputs; DI will
accept data on the falling edge of CLK-signal; see
table 3
for
input data protocol
14
OUTHS
High side switch output;
controlled via SPI, in sleep mode
controlled by internal cyclic sense function when selected
15
V
S
Power supply input
; block to GND directly at the IC with ceramic
capacitor
16
SI
Sense comparator input;
for monitoring of external voltages, to
program the detection level connect external voltage divider
5
GND
Ground;
to reduce thermal resistance place cooling areas on
PCB close to this pins.
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