
TLE 5208-6 G
Semiconductor Group
6
1998-02-01
voltage comparators with hysteresis, so that the correct function can be checked in the
application at any time.
The logic is supplied by the
V
CC
voltage, typ. with 5 V. The
V
CC
voltage uses an internally
generated Power-On Reset (POR) to initialize the module at power-on. The advantage
of this system is that information stored in the logic remains intact in the event of short-
term failures in the supply voltage
V
S
. The system can therefore continue to operate
following
V
S
under-voltage, without having to be reprogrammed. The “under-voltage”
information is stored, and can be read out via the interface. The same logically applies
for over-voltage. “Interference spikes” on
V
S
are therefore effectively suppressed.
The situation is different in the case of under-voltage on the
V
CC
connection pin. If this
occurs, then the internally stored data is deleted, and the output levels are switched to
high-impedance status (tristate). The module is initialized by
V
CC
following restart
(Power-On Reset = POR).
The 16-bit wide programming word or control word (see table at
page 8
) is read in via
the DI data input, and this is synchronized with the clock input CLK. The status word
appears synchronously at the DO data output (see table at
page 8
).
The transmission cycle begins when the chip is selected with the CSN input (H to L). If
the CSN input changes from L to H then the word which has been read-in becomes the
control word. The DO output switches to tristate status at this point, thereby releasing the
DO bus circuit for other uses.
The INH inhibit input can be used to cut off the complete module. This reduces the
current consumption to just a few
μ
A, and results in the loss of any data stored. The
output levels are switched to tristate status. The module is reinitialized with the internally
generated POR (Power-On Reset) at restart.
This feature allows the use of this module in battery-operated applications (vehicle body
control applications).
Every driver block from DRV 1 to 6 contains a low-side driver and a high-side driver. The
output connections have been selected so that each HS driver and LS driver pair can be
combined to form a half-bridge by short-circuiting adjacent connections. The full flexibility
of the configuration can be achieved by dissecting the half-bridges into “quarter-bridges”.
Figure 3
shows examples of possible applications.
When commutating inductive loads, the dissipated power peak can be significantly
reduced by activating the transistor located parallel to the internal freewheeling diode. A
special, integrated “timer” for power ON/OFF times ensures there is no crossover current
at the half-bridge.