參數(shù)資料
型號(hào)： TLC5902HTQFP
廠商： Texas Instruments, Inc.
元件分類： LED驅(qū)動(dòng)器
英文描述： LED DRIVER
中文描述： LED驅(qū)動(dòng)
文件頁(yè)數(shù)： 6/22頁(yè)
文件大?。?/td> 306K
代理商： TLC5902HTQFP
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
BC_ENA
85
I
Brightness control enable. When BC_ENA is low, the brightness control function is disabled. At
this time, the brightness control latch is reset to 1Fh. Output current value is 100% of setting value
by an external resistor and the frequency division ratio of GSCLK is 1/1.
Blank (Light off). When BLANK is high, all the output of the constant current driver is turned off.
All the output is turned on (LED on) synchronizing to the falling edge of GCLK after next rising edge
of GCLK when BLANK goes from high to low.
Blank signal delay. BOUT is output with the addition of delay time to BLANK.
BLANK
68
I
BOUT
CONDUCTIVE
PAD
57
O
package
surface
Heat sink pad
DCLK
65
I
Clock input for data transfer. The input data of DIN is synchronized to the rising edge of DCLK, and
transferred to DOUT. DCLK is valid at the rising edge after ENABLE goes low.
DIN7–DIN0
70,71,72,73,
76,77,78,79
I
Input for shift register for both gray scale data and brightness control. It is 8 bits parallel data.
DOUT7–DOUT0
47,48,49,51,
52,53,54,55
O
Output for shift register for both gray scale data and brightness control.
DOWN
60
O
Shutdown. DOWN is configured as an open collector. It goes low when the constant current output
is shut down by the WDT or TSD function.
Data transfer enable. When ENABLE is high, data is not transferred.
Analog ground. (Internally connected to GNDLOG and GNDLED)
ENABLE
GNDANA
64
43
I
GNDLED
5,10,15,20,29,
36,90,96
LED driver ground (Internally connected to GNDANA and GNDLOG)
GNDLOG
84
Logic ground. (Internally connected to GNDANA and GNDLED)
Clock input for gray scale. The gray scale display is accomplished by lighting the LED until the
number of GSCLK counted is equal to the data latched.
Clock delay for gray scale. GSOUT is output with addition of delay time to GSCLK
Constant current control setting. LED current is set to the desired value by connecting an external
resistor between IREF and GND. The 38 times current is compared to current across external
resistor sink on output terminal.
Latch. When LATCH is high, data on shift register goes through the latch. When LATCH is low, data
is latched. Accordingly, if data on the shift register is changed during LATCH high, this new value
is latched.
8/16 bits select. When the MODE is high, the 16 bits output is selected. When the MODE is low,
the 8 bits output is selected.
GSCLK
69
I
GSOUT
56
O
IREF
40
I
LATCH
61
I
MODE
83
I
OUT0–OUT15
87,93,94,100,
3,7,8,12,13,17,
18,22,26,32,
33,39
41
O
Constant current output
PVCC
LED driver power supply voltage
Shift register latch switching. When RSEL is low, the shift register and latch for gray scale are
selected. When RSEL is high, the shift register and latch for brightness control are selected.
TEST. Factory test terminal. TEST should be connected to GND for normal operation.
TSD (Thermal shutdown) enable. When TS_ENA is high, TSD is enabled. When TS_ENA is low,
TSD is disabled.
Analog power supply voltage
Logic power supply voltage
RSEL
66
I
TEST1, TEST2
88,38
I
TS_ENA
80
I
VCCANA
VCCLOG
45
81
WD_CAP
42
I
WDT detection time adjustment. The capacitor for WDT detection time adjustment is connected
between WD_CAP and GND. When WD_CAP is directly connected to GND, the WDT function
is disabled.
WDT scan input. By applying a scan signal to this terminal, the scan signal can be monitored and
constant current output can be turned off. LED is protected from damage from burning when the
scan signal is stopped during the constant period. The scan signal should be applied to this
terminal by connecting W_CAP to GND even though no WDT function is used.
WD
62
I
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