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    參數(shù)資料
    型號: TLC5615IP
    廠商: TEXAS INSTRUMENTS INC
    元件分類: DAC
    英文描述: SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDIP8
    封裝: ROHS COMPLIANT, PLASTIC, DIP-8
    文件頁數(shù): 2/22頁
    文件大?。?/td> 552K
    代理商: TLC5615IP
    www.ti.com
    SCLK
    DIN
    CS
    DOUT
    TLC5615
    SK
    SO
    I/O
    SI
    Microwire
    Port
    NOTE A: The DOUT-SI connection is not required for writing to
    the TLC5615 but may be used for verifying data
    transfer if desired.
    SCLK
    DIN
    CS
    DOUT
    TLC5615
    SCK
    MOSI
    I/O
    MISO
    SPI/QSPI
    Port
    NOTE A: The DOUT-MISO connection is not required for writing to the
    TLC5615 but may be used for verifying data transfer.
    CPOL = 0, CPHA = 0
    DAISY-CHAINING DEVICES
    LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE-ENDED SUPPLIES
    SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
    The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width.
    When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer
    requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT
    terminal (see Figure 1).
    The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data
    converter transfers.
    The TLC5615 three-wire interface is compatible with the SPI, QSPI, and Microwire serial standards. The
    hardware connections are shown in Figure 12 and Figure 13.
    The SPI and Microwire interfaces transfer data in 8-bit bytes; therefore, two write cycles are required to input
    data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
    input register in one write cycle.
    Figure 12. Microwire Connection
    Figure 13. SPI/QSPI Connection
    DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the
    chain, providing that the setup time, tsu(CSS) (CS low to SCLK high), is greater than the sum of the setup time,
    tsu(DS), plus the propagation delay time, tpd(DOUT), for proper timing (see digital input timing requirements section).
    The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poled
    output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUT
    remains at the value of the last data bit and does not go into a high-impedance state.
    When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative.
    With a positive offset, the output voltage changes on the first code change. With a negative offset the output
    voltage may not change with the first code depending on the magnitude of the offset voltage.
    10
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