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參數(shù)資料
| 型號： | TLC5615IDGKRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 504K |
| 代理商： | TLC5615IDGKRG4 |
www.ti.com
OPERATING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
th(CSH0)
tsu(CSS)
tw(CH)
tw(CL)
th(CSH1)
tsu(CS1)
tw(CS)
tpd(DOUT)
CS
SCLK
DIN
DOUT
tsu(DS)
th(DH)
NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.
See Note A
See Note B
MSB
LSB
B. Data input from preceeding conversion cycle.
See Note C
Previous LSB
C. Sixteenth SCLK falling edge
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
over recommended operating free-air temperature range, V
DD = 5V ±5%, Vref = 2.048V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT DYNAMIC PERFORMANCE
CL = 100pF,
SR
Output slew rate
RL = 10k,
0.3
0.5
V/
s
TA= +25°C
To 0.5LSB,
ts
Output settling time
CL = 100pF, (1)
12.5
s
RL = 10k,
Glitch energy
DIN = All 0s to all 1s
5
nV-s
REFERENCE INPUT (REFIN)
Reference feedthrough
REFIN = 1VPP at 1kHz + 2.048Vdc (2)
–80
dB
Reference input
REFIN = 0.2VPP + 2.048Vdc
30
kHz
bandwidth (f–3dB)
(1)
Settling time is the time for the output signal to remain within
±0.5LSB of the final measured value for a digital input code change of 000
hex to 3FF hex or 3FF hex to 000 hex.
(2)
Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048Vdc + 1Vpp at 1kHz.
Figure 1. Timing Diagram
5
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