參數(shù)資料
型號： TLC3545IDGKRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： GREEN, PLASTIC, MSOP-8
文件頁數(shù)： 23/26頁
文件大小： 661K
代理商： TLC3545IDGKRG4
TLC3541, TLC3545
SLAS345 DECEMBER 2001
6
www.ti.com
timing requirements, VDD = 5 V, VREF = 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified)
MIN
TYP
MAX
UNIT
tcyc(SCLK) SCLK cycle time, VDD = 4.5 V to 5.5 V (see Note 3)
66
10000
ns
tw1
Pulse duration, SCLK low
27
5000
ns
tw2
Pulse duration, SCLK high
27
5000
ns
th1
Hold time, CS high after SCLK falling edge
3
ns
tsu1
Setup time, CS falling edge before the first SCLK falling edge
15
ns
th2
Hold time, CS low after 16th SCLK falling edge
5
ns
tw3
Pulse duration, CS high
0.5
SCLKs
td1
Delay time, CS falling edge to SDO MSB valid, VDD = VREF = 4.5 V, 20 pF
12
17
ns
td2
Delay time, SCLK rising edge to next SDO data bit valid, VDD = VREF = 4.5 V, 20 pF
15
ns
td3
Delay time, 17th SCLK rising edge to 3-stated SDO, VDD = VREF = 4.5 V, 20 pF (see Note 4)
20
ns
tsu3
Setup time, CS falling edge before FS rising edge (TLC3541 only)
0.5
1
SCLKs
tw4
Pulse duration, FS high (TLC3541 only)
0.5
1
SCLKs
tsu4
Setup time, FS rising edge before SCLK falling edge (TLC3541 only)
12.5
ns
th4
Hold time, FS high after SCLK falling edge (TLC3541 only)
5
ns
tsu5
Setup time, FS falling edge before 1st SCLK falling edge (TLC3541 only)
12
ns
td4
Delay time, FS rising edge to SDO MSB valid, (VDD = VREF = 4.5 V, 20 pF TLC3541 only)
15
ns
th6
Hold time, CS low after 1st SCLK falling edge
5
ns
tsu6
Setup time, CS rising edge before 9th (or the last) SCLK falling edge
5
ns
th7
Hold time, FS low after 1st SCLK falling edge (TLC3541 only)
5
ns
tsu7
Setup time, FS rising edge before 9th (or the last) SCLK falling edge
5
ns
tcyc(reset)
Active CS/FS cycle time, SCLK falling edges required to initialize ADC
1
8
SCLKs
tconv
Conversion time (20 conversion clocks based on 7.5 MHz to 12 MHz OSC)
1.67
2.67
s
ts
Sample time, 20 SCLKs, SCLK up to 15 MHz
1.33
200
s
NOTES:
3. Timing specifications given for 40/60 to 60/40 duty cycle
4. SDO goes into the high impedance state after detection of the 17th rising SCLK edge or a rising CS edge if a 17th SCLK is not
presented.
相關(guān)PDF資料
PDF描述
TLC3548CPW 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3548IDW 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3548IPW 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3548CDWR 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3548CPWR 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC3545IDR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-Bit 200KSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
TLC3545IDRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-Bit 200KSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
TLC3548 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
TLC3548CDW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-bit 5V 200KSPS 8-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
TLC3548CDWG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-bit 5V 200KSPS 8-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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