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參數(shù)資料
| 型號： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 26/60頁 |
| 文件大?。?/td> | 408K |
| 代理商： | TLC34076-170 |
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2–9
Mode 6b is the XGA-compatible (5-6-5) true color mode. This 16-bit mode has 5 bits of red, 6 bits of green,
and 5 bits of blue data. The overlay function is not enabled in this mode. Refer to Table 2–8 for the exact
bit definitions.
Mode 6c is a multiplexed version of mode 6a that allows two 16-bit TARGA-compatible words to be latched
into the TLC34076-170 pixel port with one SCLK. In this mode, the 16-bit word latched on pixel port inputs
P0-P15 is executed first, while the word latched on P16-P31 is executed last. The user should program the
SCLK divide ratio in the output-clock selection register to two. Refer to Table 2–8 for the exact bit definitions.
Mode 6d is a multiplexed version of mode 6b that allows two 16-bit XGA-compatible words to be latched
into the TLC34076-170 pixel port with one SCLK. In this mode, the 16-bit word latched on pixel port inputs
P0-P15 is executed first, while the word latched on P16-P31 is executed last. The user should program the
SCLK divide ratio in the output-clock selection register to two. Refer to Table 2–8 for the exact bit definitions.
Mode 6e is a 24-bit true color mode that features 8 bits of data for each color, as well as 8 bits of overlay
information. The order in which the color and overlay fields appear in the 32-bit word are the reverse of
mode 6f. Refer to Table 2–8 for the exact bit definitions.
Mode 6f is the 24-bit true color mode used on the TLC34076-170. It also features eight bits of data for each
color, as well as eight bits of overlay information. Refer to Table 2–8 for the exact bit definitions.
Since only 5 bits (6 bits for green in Modes 6b and 6d) are provided for each color in the 16-bit true color
modes (6a–6d), the color data is internally shifted by the TLC34076-170 to the 5 MSB positions (6 MSB
positions for green in Modes 6b and 6d) before being presented to the three color DACs. The remaining
lower 3 bits (Iower 2 bits for green in Modes 6b and 6d) are then set to logic 0.
When in true color modes 6a or 6c, the internal palette page register fills the remaining seven MSBs of
overlay data (see Section 2.2.3). This occurs because, in these modes, there is only one bit of overlay
information presented in the true color word. In order to enable the true color data to the DACs, all eight
overlay bits must be at logic zero. This can be accomplished by either writing zeros to the internal palette
page register and the overlay bit, or by writing zeros to the internal read mask (see Section 2.4.6).
When in true color modes 6e or 6f, the data input only works in the 8-bit mode. In other words, if only six
bits are to be used, the two LSB inputs for each color must be tied to GND. However, the palette, which is
used by the overlay input, is still governed by the 8/6-input terminal, and the output multiplexer selects eight
bits of data or six bits of data accordingly. The 8/6-input terminal is also valid in the other 16-bit modes.
Both little- (default) and big-endian data formats are supported by the true color modes (see Section 2.6 and
Table 2–8 for more information).
2.4.5
Multiplex Control Register
The multiplexer is controlled by the 8-bit multiplex control register. The bit fields of the register are in
Table 2–6 and Table 2–7.
As an example of how to use Table 2–6, suppose that the design goals specify a system with eight data bits
per pixel and the lowest possible SCLK rate. Table 2–6 shows that for non-VGA-pass-through operation,
only mode 4 supports an 8-bit pixel depth. The lowest-possible SCLK rate within mode 4 is 1:4. This set of
conditions is selected by writing the value 1Eh to the multiplex control register. The pixel latching sequence
column shows that in this mode, P<7:0> should be connected to the earliest-displayed pixel plane followed
by P<15:8>, P<23:16> and then P<31:24> as the last displayed pixel plane. Assuming that VCLK is
programmed as DOTCLK/4, Table 2–5 shows that the 1:4 SCLK ratio is selected by writing the value 12h
to the output clock selection register. The special nibble mode should also be disabled (see Section 2.9.2).
When the multiplex control register is loaded with 2Dh, the TLC34076-170 enters the VGA pass-through
mode (the same condition as the default power-up mode). Refer to Section 2.5.4 for more details.
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