參數(shù)資料
    型號: TLC34075A-135
    廠商: Texas Instruments, Inc.
    英文描述: Color-Palette(135MHz,視頻接口調色器)
    中文描述: 顏色調色板(135MHz,視頻接口調色器)
    文件頁數(shù): 28/53頁
    文件大小: 394K
    代理商: TLC34075A-135
    2-15
    SCLK
    Input
    SFLAG/NFLAG
    Register Bit 2)
    (General Control
    SSRT Enable
    BLANK
    Figure 2–9. Relationship Between SFLAG/NFLAG, BLANK, and SCLK
    If SFLAG/NFLAG is designed as an R-S latch set by split shift register transfer timing and reset by BLANK
    going high, the delay from BLANK high to SFLAG/NFLAG low cannot exceed one-half of one SCLK cycle;
    otherwise, the SCLK generation logic may fail.
    If the SSRT function is enabled but SFLAG/NFLAG is held low, SCLK runs as if the SSRT function is
    disabled. The SFLAG/NFLAG input is not qualified by the BLANK signal and needs to be held low whenever
    an SSRT SCLK pulse is not desired. Refer to Section 2.3.1 and Figures 2–2 through 2–8 for more system
    details.
    2.9.2
    Special Nibble Mode
    Special nibble mode is enabled when the SNM bit (bit 3 in the general control register) is set to 1 and the
    SSRT bit (bit 2 in the general control register) is reset to 0 (see Section 2.11). Special nibble mode provides
    a variation of the 4-bit pixel mode with a 16-bit bus width. While all 32 inputs (P<0:31>) are connected as
    4 bytes, the 16-bit data bus is composed of the lower or upper nibble of each of the 4 bytes, depending on
    the level of the SFLAG/NFLAG input. The pixel data is distributed to 16-bit data bus as shown in Table 2–7.
    Table 2–7. Pixel Data Distribution in Special Nibble Mode
    SNM BIT = 1, SSRT BIT = 0
    SFLAG/NFLAG = 1
    P<7:4>
    P<15:12>
    P<23:20>
    P<31:28>
    SFLAG/NFLAG = 0
    P<3:0>
    P<11:8>
    P<19:16>
    P<27:24>
    The SFLAG/NFLAG value is not latched by the TLC34075A. Therefore, it should stay at the same level
    during the whole active display period, changing levels only during the BLANK signal active time. Refer to
    Figure 2–10, which is similar to Figure 2–2 except that the BLANK signal timing reference to SFLAG/NFLAG
    is explained. The SFLAG/NFLAG input has to meet the setup time and hold the data long enough to ensure
    that no pixel data is missed.
    Special nibble mode operates at the line frequency when BLANK is active. However, the typical application
    of this mode is double frame buffers with pixel data width of 4 bits. While one frame buffer is being displayed
    on the monitor, the other frame buffer can be used to accept new picture information. SFLAG/NFLAG is used
    to indicate which frame buffer is being displayed.
    SNM and SSRT must be mutually exclusive. Unpredictable operation occurs if both the SNM and SSRT bits
    are set to 1. The mux control register should be set up as shown in Table 2–6 (see Section 2.4.5). However,
    the SNM bit takes precedence over the other mux control register selections. In other words, if the mux
    control register is set up for another mode but special nibble mode is still enabled in the general control
    register, the input multiplex circuit takes whatever SCLK divide ratio the mux control register specifies and
    performs the nibble operation, causing operational failure.
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