
2
–
16
During special nibble mode, the input mux circuit latches all 8-bit inputs but only passes on the specified
nibble. The specified nibble is stored in the 4 LSBs of the next register pipe after the input latch, and the
4 MSBs are zeroed in that register. The register pipe contents are then passed to the read mask block. With
this structure, the palette page register still functions normally, providing good flexibility to users.
If the general control register bit 3 = 0 and bit 2 = 0, both split shift register transfers and special nibble mode
are disabled and the SFLAG/NFLAG input is ignored.
Sampled
BLANK
LOAD
Input
SFLAG/NFLAG
of Pixel Data
Latch First Group
of Pixel Data
Latch Last Group
Valid
Don
’
t Care
Valid
(at its input pin)
Last Group of Pixel Data
SCLK
PIXEL DATA
BLANK
VCLK
CAUTION:
If the data is not held valid until SCLK and BLANK both go low, the last few pixels could be missed.
Setup time to next VCLK falling edge after BLANK high (must be met, otherwise the first pixel data
could be missed).
Group
2nd
Group
1st
Group
4th
Group
3rd
Group
5th
Figure 12. SFLAG/NFLAG Timing in Special Nibble Mode
2.10
MUXOUT is a TTL-compatible output. It is software programmable and is used to control external devices.
Its typical application is to select the HSYNC and VSYNC inputs between the VGA pass-through mode and
the normal modes (see Section 2.8). This output is driven low at power-up or when VGA pass-through mode
is selected; at any other time it can be programmed to the desired polarity via general control register bit
7.
MUXOUT Output
2.11
The general control register is used to control HSYNC and VSYNC polarity, split shift register transfer
enabling, special nibble mode, sync control, the ones accumulation clock source, and the VGA
pass-through indicator. The bit field definitions are as follows:
General Control Register