參數(shù)資料
型號(hào)： TLC320AD77CDBRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： GREEN, PLASTIC, SSOP-28
文件頁(yè)數(shù)： 3/33頁(yè)
文件大?。?/td> 391K
代理商： TLC320AD77CDBRG4
2–1
2 Functional Description
2.1
ADC Channel
To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data. A single-ended input signal must be converted into a
differential input and filtered with a single-pole antialiasing filter before entering the ADC input. (See
Section 2.7,
ADC Analog Input). The ADC converts the signal into discrete output digital words in
2s-complement format, corresponding to the analog signal input. There is a high-pass filter to get rid of any
offset that the ADC modulator may have caused. These digital words, representing sampled values of the
analog input signal, are then clocked out the serial port, SDOUT, according to one of the eight allowable
serial port protocols.
2.2
DAC Channel
SDIN receives a serial data word whose length is specified by one of the eight allowable serial port protocols,
selected by the serial mode pins. The serial port latches the data on an edge of SCLK. The data goes through
the sigma-delta DAC comprised of digital interpolation filters and a seventh order, 1-bit digital modulator.
This oversampled signal is then passed through a switched capacitor FIR filter and RC low-pass filter which
smoothes the output waveform, and performs the differential to single-ended conversion. The DAC outputs
a stereo single-ended, inverted signal. This signal should be passed through an inverting,
pseudo-differential, external low-pass filter, where the VCOM reference is subtracted out. (See Section 2.8,
DAC Analog Output).
2.3
Serial Interface
The digital serial interface consists of a serial port, shift clock (SCLK), left/right frame synchronization clock
(LRCLK), ADC-channel data output (SDOUT), and DAC-channel data input (SDIN). One of 8 different serial
port modes may be selected including IIS, right/left justified, left/left justified, and a DSP mode for word
lengths ranging from 16 to 24 bits. See Section 2.14,
Serial Interface Formats for a description of serial
interface formats.
2.4
Sampling Frequency
The sampling or conversion frequency is designated by the MCLK rate by the following equation.
fs = MCLK frequency/ (256 or 384).
See Section 2.14,
Serial Interface Formats for more information on the option of selecting an MCLK rate
of 256 fs or 384 fs.
2.5
Speed Mode Options
In normal-speed mode (SPDMOD = 0), sampling frequencies ranging from 16 kHz up to 48 kHz should be
used to achieve optimum performance.
In high-speed mode (SPDMOD = 1) the sampling frequencies are greater than 48 kHz and up to 96 kHz.
2.6
Voltage Reference
In order to achieve excellent noise rejection, a pseudo-differential reference is used with external capacitors
connected to a differential low-pass filter. The application schematic shows the necessary capacitors
needed to complete the filters found on the device. See Section 5,
Application Information for the application
schematic for the voltage reference.
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