參數(shù)資料
型號: TLC320AD77C
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: 24-BIT 96 kHz STEREO AUDIO CODEC
中文描述: 24位96千赫立體聲音頻編解碼
文件頁數(shù): 12/31頁
文件大小: 215K
代理商: TLC320AD77C
2–2
2.7
The ADC accepts a differential input with a maximum value that does not exceed approximately 4 V
pp
. See
Section 5.1, Single-Ended to Differential External Analog Front-End Circuitfor a description of the
recommended external analog front end.
ADC Analog Input
2.8
The DAC outputs a single-ended signal with a max value of 0.7 Vrms. See Section 5.2, External Analog
Back-End Circuitfor a description of the recommended back-end circuit.
DAC Analog Output
2.9
The sigma-delta ADC is a third order modulator with 128 times oversampling in normal speed operation.
The ADC provides high resolution and low noise performance using over-sampling techniques.
Sigma-Delta ADC
2.10 Decimation Filter
The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating
with a ratio of 1:128. The output of this filter is a 2s complement 16-, 20-, 24-bit word clocking at the sample
rate selected.
2.11 Sigma-Delta DAC
The sigma-delta DAC is a seventh order modulator with 128 times oversampling. The DAC provides
high-resolution, low noise, from a 1-bit converter using over-sampling techniques.
2.12 Interpolation Filter
The interpolation filter resamples the digital data at a rate 128 times the incoming sample rate. The
high-speed data output is then used in the sigma-delta DAC.
2.13 De-emphasis
De-emphasis is supported for three sampling rates: 32 kHz, 44.1 kHz, and 48 kHz and selected with the
DEM0 and DEM1 pins.
2.14 Serial Interface Formats
The TLC320AD77C operates only in slave mode. It requires externally supplied MCLK (master clock), and
LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options for selecting the clock rates.
If a 384 f
s
MCLK rate is selected, then a LRCLK frame of 48 SCLKs must be supplied. If a 256 f
s
MCLK is
selected, then a LRCLK of 64 SCLKs must be supplied.
A detection circuit automatically senses at which rate the MCLK is operating.
The MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.
If the LRCLK phase changes more than 10 MCLKs then the device automatically resets.
The TLC320AD77C is compatible with eight different serial interfaces. Available interface options are IIS,
right justified, left justified, and DSP frame. The following table indicates how the eight options are selected
using the MOD0, MOD1, and MOD2 pins. All serial interface options at either 16-, 20-, or 24-bits can operate
with SCLK at 48*f
s
or 64*f
s
except for the 16-bit DSP mode which should use SCLK = 64 f
s
.
相關(guān)PDF資料
PDF描述
TLC320AD80C Audio Processor Subsystem
TLC320AD81CDBT Stereo Audio Digital Equalizer DC
TLC320AD81C Stereo Audio Digital Equalizer DC
TLC339CDB LinCMOSE MICROPOWER QUAD COMPARATORS
TLC339CDBR LinCMOSE MICROPOWER QUAD COMPARATORS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC320AD77CDB 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD77CDBG4 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD77CDBR 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD77CDBRG4 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD80C 制造商:TI 制造商全稱:Texas Instruments 功能描述:Audio Processor Subsystem