參數(shù)資料
型號(hào)： TLC320AD55CDWR
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： PLASTIC, SOP-28
文件頁(yè)數(shù)： 2/41頁(yè)
文件大小： 203K
代理商： TLC320AD55CDWR
1–4
1.5
Terminal Functions
TERMINALS
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AUXM
27
I
Inverting input to auxiliary analog input
AUXP
28
I
Noninverting input to auxiliary analog input
ALT DATA
18
I
Signals on ALT DATA are routed to DOUT during secondary communiction when phone
mode is enabled.
DIN
10
I
Data input. DIN receives the DAC input data and command information from the DSP
and is synchronized to SCLK.
DOUT
11
O
Data output. DOUT transmits the ADC output bits and is synchronized to SCLK. DOUT
is at Hi-Z when FS is not activated.
DVDD
9
I
Digital power supply
DVSS
20
I
Digital ground
FC
15
I
Function control. FC is sampled and latched on the rising edge of FS for the primary serial
communication. Refer to Section 3 Serial Communications for more details.
FLAG 0
17
O
During phone mode, FLAG 0 contains the value set in control 2 register.
FLAG 1
16
O
During phone mode, FLAG 1 contains the value set in control 2 register.
FS
12
O
Frame sync. When FS goes low, the serial communication port is activated. In all serial
transmission modes, FS is held low during bit transmission. Refer to Section 3 Serial
Communications for a detailed description.
INM
25
I
Inverting input to analog input
INP
26
I
Noninverting input to analog input
MCLK
14
I
Master clock. MCLK derives the internal clocks of the sigma-delta analog interface
circuit.
OUTM
4
O
Inverting output of the DAC analog power amplifier. Functionally identical with and
complementary to OUTP. OUTM and OUTP can drive 600
differentially. OUTM should
not be used alone for single-ended operation.
OUTP
3
O
Noninverting output of the DAC analog power amplifier. OUTM and OUTP can drive
600
differentially. OUTP should not be used alone for single-ended operation.
PWRDWN
2
I
Power down. When PWRDWN is pulled low, the device goes into a power-down mode;
the serial interface is disabled and most of the high-speed clocks are disabled. However,
all of the registers’ values are sustained and the device resumes full power operation
without reinitialization when PWRDWN is pulled high again. PWRDWN resets the
counters only and preserves the programmed register contents. Refer to Section 2.2.1.3
Software and Hardware Power-Down.
REFCAPADC
23
O
Analog-reference voltage connection for external capacitor for the ADC. The nominal
voltage on REFCAPADC is 3.4 V. A buffer must be used when this voltage is used
externally. REFCAPADC is not to be used as the mid-supply voltage reference for
single-ended operation.
REFCAPDAC
6
O
Analog-reference voltage connection for external capacitor for the DAC. The nominal
voltage on REFCAPDAC is 3.4 V. A buffer must be used when this voltage is used
externally.
RESET
8
I
Reset. The reset function initializes all of the internal registers to their default values. The
serial port can be configured to the default state accordingly. Refer to Appendix A Table
A–2 Control 1 Register and Section 2.2.1 Reset and Power-Down for more detailed
descriptions.
SCLK
13
O
Shift clock. SCLK is derived from MCLK and clocks serial data into DIN and out of DOUT.
NOTE 1: All digital inputs and outputs are TTL compatible unless otherwise noted.
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