參數(shù)資料
型號： TLC320AC02IFN
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQCC28
封裝： PLASTIC, LCC-28
文件頁數(shù)： 5/86頁
文件大?。?/td> 471K
代理商： TLC320AC02IFN
1–7
A Register
(8 bits)
Divide by 2
576 kHz
B Register
(8 bits)
Divide by 4
1.296 MHz
2.592 MHz
5.184 MHz
10.368 MHz
MCLK
Processor
SCLK
A Register + A
′ Register
(8 bits)
2s Complement
Program Divide
A Counter
(8 bits)
B Counter
288 kHz
FCLK [low-pass filter and
(sin x)/x filter clock]
Conversion
Rate
Single, A-Counter
Period
One-Shot
Phase Shift
Normal
Control
Figure 1–1. Control Flow Diagram
Table 1–1. Operating Frequencies
FCLK
(kHz)
LOW-PASS FILTER
BANDWIDTH
(kHz)
B REGISTER CONTENTS
(Program No. of Filter Clocks)
(Decimal)
CONVERSION
RATE
(kHz)
HIGH-PASS
POLE FREQUENCY
(Hz)
144
3.6
20 (see Note 1)
18
15
10 (see Note 2)
7.2
8
9.6
14.4
36
40
48
72
288
7.2
20 (see Note 1)
18
15
10 (see Notes 2 and 3)
14.4
16
19.2
28.8
72
80
96
144
432
10.8
20 (see Note 1)
18
15 (see Note 3)
10 (see Notes 2 and 3)
21.6
24
28.8
43.2
108
120
144
216
NOTES:
1. The B register can be programmed for values greater than 20; however, since the sample rate is lower than
7.2 kHz and the internal filter remains at 3.6 kHz, an external antialiasing filter is required.
2. When the B register is programmed for a value less than 10, the ADC and the DAC conversions are not
completed before the next frame-sync signal and the results are in error.
3. The maximum sampling rate for the ADC channel is 43.2 kHz. The maximum rate for the DAC channel is
25 kHz.
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