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參數(shù)資料
| 型號(hào)： | TLC32046C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Wide-Band Analog Interface Circuit |
| 中文描述： | 寬帶模擬接口電路 |
| 文件頁數(shù)： | 24/57頁 |
| 文件大?。?/td> | 297K |
| 代理商： | TLC32046C |
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2–10
2.15.3
D/A MSB
Secondary DX Word Bit Pattern
1st bit sent
↓
D15
1st bit sent of 2nd byte
↓
D8
D7
D/A LSB
↓
D2
D14
D13
D12
D11
D10
D9
D6
D5
D4
D3
D1
D0
Table 2–3. Secondary DX Serial Communication Protocol
FUNCTIONS
D1
D0
D13 (MSB)-D9
→
TA , 5 bits unsigned binary (see Figure 2–1).
D6 (MSB)-D2
→
RA, 5 bits unsigned binary (see Figure 2–1).
D15, D14, D8, and D7 are unassigned.
D14 (sign bit)-D9
→
TA
′
, 6 bits 2s complement (see Figure 2–1).
D7 (sign bit)-D2
→
RA
′
, 6 bits 2s complement (see Figure 2–1).
D15 and D8 are unassigned.
D14 (MSB)-D9
→
TB, 6 bits unsigned binary (see Figure 2–1).
D7 (MSB)-D2
→
RB, 6 bits unsigned binary (see Figure 2–1).
D15 and D8 are unassigned.
0
0
0
1
1
0
D2 = 0/1 deletes/inserts the A/D high-pass filter.
D3 = 0/1 deletes/inserts the loopback function.
D4 = 0/1 disables/enables AUX IN+ and AUX IN–.
D5 = 0/1 asynchronous/synchronous transmit and receive sections.
D6 = 0/1 gain control bits (see Table 4–1).
D7 = 0/1 gain control bits (see Table 4–1).
D9 = 0/1 delete/insert on-board second-order (sinx)/x correction filter
D10 = 0/1 output to D10OUT (dual-word (telephone interface) mode)
D11 = 0/1 output to D11OUT (dual-word (telephone interface) mode)
D8, D12–D15 are unassigned.
1
1
2.16 Reset Function
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function
initializes all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on RESET initializes the AIC registers to provide a 16-kHz A/D and D/A conversion
rate for a 10.368-MHz master clock input signal. Also, the pass-bands of the A/D and D/A filters are 300
Hz to 7200 Hz and 0 Hz to 7200 Hz, respectively; therefore, the filter bandwidths are half those shown in
the filter transfer function specification section. The AIC, except the CONTROL register, is initialized as
follows (see AIC DX Data Word Format section):
REGISTER
INITIALIZED VALUE (HEX)
TA
12
TA
′
01
TB
12
RA
12
RA
′
01
RB
12
The CONTROL register bits are reset as follows (see Table 2–3):
D11 = 0, D10 = 0, D9 = 1, D7 = 1, D6 = 1, D5 = 1, D4 = 0, D3 = 0, D2 = 1
This initialization allows normal serial port communications to occur between the AIC and the DSP. If the
transmit and receive sections are configured to operate synchronously and the user wishes to program
different conversion rates, only the TA, TA
′
, and TB register need to be programmed. Both transmit and
receive timing are synchronously derived from these registers (see the Terminal Functions and DX Serial
Data Word Format sections).
Figure 2–3 shows a circuit that provides a reset on power-up when power is applied in the sequence given
in the power-up sequence section. The circuit depends on the power supplies reaching their recommended
values a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
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