
TLC32040C, TLC32040I, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
serial port recommended input signals
MIN
MAX
UNIT
tc(MCLK)
tr(MCLK)
tf(MCLK)
Master clock cycle time
95
ns
Master clock rise time
10
ns
Master clock fall time
10
ns
Master clock duty cycle
42%
58%
RESET pulse duration (see Note 12)
DX setup time before SCLK
↓
DX hold time after SCLK
↓
800
ns
tsu(DX)
th(DX)
20
ns
tc(SCLK)/4
ns
serial port – AIC output signals, C
L
= 30 pF for SHIFT CLK output, C
L
= 15 pF for all other outputs
MIN
TYP
MAX
UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
380
ns
Shift clock (SCLK) fall time
3
8
ns
Shift clock (SCLK) rise time
3
8
ns
Shift clock (SCLK) duty cycle
Delay from SCLK
↑
to FSR/FSX/FSD
↓
Delay from SCLK
↑
to FSR/FSX/FSD
↑
DR valid after SCLK
↑
Delay from SCLK
↑
to EODX/EODR
↓
in word mode
Delay from SCLK
↑
to EODX/EODR
↑
in word mode
EODX fall time
45
55
%
td(CH-FL)
td(CH-FH)
td(CH-DR)
td(CH-EL)
td(CH-EH)
tf(EODX)
tf(EODR)
td(CH-EL)
td(CH-EH)
td(MH-SL)
td(MH-SH)
Typical values are at TA = 25
°
C.
NOTE 12: RESET pulse duration is the amount of time that the reset terminal is held below 0.8 V after the power supplies have reached their
recommended values.
30
ns
35
90
ns
90
ns
90
ns
90
ns
2
8
ns
EODR fall time
Delay from SCLK
↑
to EODX/EODR
↓
in byte mode
Delay from SCLK
↑
to EODX/EODR
↑
in byte mode
Delay from MSTR CLK
↑
to SCLK
↓
Delay from MSTR CLK
↑
to SCLK
↑
2
8
ns
90
ns
90
ns
65
170
ns
65
170
ns