參數(shù)資料
型號： TLC32040MJ
廠商： Texas Instruments, Inc.
英文描述： ANALOG INTERFACE CIRCUIT
中文描述： 模擬接口電路
文件頁數(shù)： 4/30頁
文件大?。?/td> 202K
代理商： TLC32040MJ
DESCRIPTION
I/O
TLC32040M
ANALOG INTERFACE CIRCUIT
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4–4
Terminal Functions (Continued)
PIN
NAME
NO.
10
SHIFT CLK
O
The shift clock signal is obtained by dividing the master clock signal frequency by four. This signal is used to clock
the serial data transfers of the AIC, described in the WORD/BYTE description (see the Serial Port Timing and
Internal Timing Configuration diagrams).
Digital supply voltage, 5 V
±
5%
Positive analog supply voltage, 5 V
±
5%
Negative analog supply voltage, –5 V
±
5%
This terminal, in conjunction with a bit in the control register, is used to establish one of four serial modes. These
four modes are described below.
AIC transmit and receive sections are operated asynchronously.
The following description applies when the AIC is configured to have asynchronous transmit and receive sections.
If the appropriate data bit in the control register is a 0 (see the AIC DX data word format), the transmit and receive
sections will be asynchronous.
L
Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit bytes.
The operation sequence is as follows (see Serial Port Timing diagrams)
.
1.
FSX or FSR is brought low.
2.
One 8-bit byte is transmitted or one 8-bit byte is received.
3.
EODX or EODR is brought low.
4.
FSX or FSR emits a positive frame-sync pulse that is four shift-clock cycles wide.
5.
One 8-bit byte is transmitted or one 8-bit byte is received.
6.
EODX or EODR is brought high.
7.
FSX or FSR is brought high.
H
Serial port directly interfaces with the serial port of the SMJ32020, SMJ320C25, or SMJ320C30 and
communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing
diagrams):
1.
FSX or FSR is brought low.
2.
One 16-bit word is transmitted or one 16-bit word is received.
3.
FSX or FSR is brought high.
4
EODX or EODR emits a low-going pulse.
AIC transmit and receive sections are operated synchronously.
If the appropriate data bit in the control register is a 1, the transmit and receive sections will be configured to be
synchronous. In this case, the band-pass switched-capacitor filter and the A/D conversion timing will be derived
from TX Counter A, TX Counter B, and TA, TA’, and TB registers, rather than the RX Counter A, RX Counter B,
and RA, RA’, and RB registers. In this case, the AIC FSX and FSR timing will be identical during primary data
communication; however, FSR will not be asserted during secondary data communication since there is no new
A/D conversion result. The synchronous operation sequences are as follows (see Serial Port Timing diagrams ).
L
Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit bytes. The
operation sequence is as follows (see Serial Port Timing diagrams).
1.
FSX or FSR are brought low.
2.
One 8-bit byte is transmitted and one 8-bit byte is received.
3.
EODX and EODR are brought low.
4.
FSX and FSR emit positive frame-sync pulse that are four shift-clock cycles wide.
5.
One 8-bit byte is transmitted and one 8-bit byte is received.
6.
EODX or EODR are brought high.
7.
FSX or FSR are brought high.
H
Serial port directly interfaces with the serial port of the SMJ32020, SMJ320C25, or SMJ320C30 and
communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing
diagrams):
1.
FSX and FSR are brought low.
2.
One 16-bit word is transmitted and one 16-bit word is received.
3.
FSX and FSR are brought high.
4.
EODX or EODR emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port, with additional NOR
and AND gates, will interface to two SN54299 serial-to-parallel shift registers. Interfacing the AIC to the SN54299
shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel data bus communications
between the AIC and the digital signal processor. The operation sequence is the same as the above sequence
(see Serial Port Timing diagrams).
VDD
VCC+
VCC–
WORD/BYTE
7
20
19
13
I
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