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參數(shù)資料
| 型號： | TLC2933PWLE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| 中文描述： | 高性能鎖相環(huán) |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 367K |
| 代理商： | TLC2933PWLE |
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
2.85
NOM
MAX
3.15
UNIT
Supply voltage VDD(each supply see Note 3)
Supply voltage, VDD (each supply, see Note 3)
VDD = 3 V
VDD = 5 V
3
V
4.75
5
5.25
Input voltage, VI (inputs except VCO IN)
Output current, IO (each output)
VCO control voltage at VCO IN
0
VDD
±
2
VDD
55
V
0
mA
1
V
Lock frequency
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
37
MHz
43
100
Bias resistor RBIAS
Bias resistor, RBIAS
1.8
2.7
k
2.2
3
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and
separated from each other.
electrical characteristics over recommended operating free-air temperature range, V
DD
= 3 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
VIT+
II
Zi(VCO IN)
IDD(INH)
IDD(VCO)
NOTES:
High-level output voltage
IOH = –2 mA
IOL = 2 mA
2.4
V
Low-level output voltage
0.3
V
Positive input threshold voltage at TEST, VCO INHIBIT
0.9
1.5
2.1
±
1
V
μ
A
M
μ
A
mA
Input current at TEST, VCO INHIBIT
VI = VDD or ground
VCO IN = 1/2 VDD
See Note 4
Input impedance at VCO IN
10
VCO supply current (inhibit)
0.01
1
VCO supply current
See Note 5
5.1
15
4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, RBIAS = 2.4 k
, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
High-level output voltage
IOH = –2 mA
IOL = 2 mA
PFD INHIBIT = high,
VI = VDD or ground
2.7
V
Low-level output voltage
0.2
V
IOZ
High-impedance-state output current
±
1
μ
A
VIH
VIL
VIT+
Ci
Zi
IDD(Z)
IDD(PFD)
NOTES:
High-level input voltage at FIN–A, FIN–B
2.1
V
Low-level input voltage at FIN–A, FIN–B
0.9
V
Positive input threshold voltage at PFD INHIBIT
0.9
1.5
2.1
V
Input capacitance at FIN–A, FIN–B
5
pF
M
μ
A
mA
Input impedance at FIN–A, FIN–B
10
High-impedance-state PFD supply current
See Note 6
0.01
1
PFD supply current
See Note 7
0.7
4
6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
7. The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT
open, and VCO OUT is inhibited.
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