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參數(shù)資料
| 型號： | TLC2543MFK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| 中文描述： | 12位模擬數(shù)字轉(zhuǎn)換器與串行控制和11個模擬輸入 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 431K |
| 代理商： | TLC2543MFK |
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TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1–9,
11, 12
AIN0 – AIN10
I
Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should
be less than or equal to 50
for 4.1-MHz I/O CLOCK operation and be
capable of slewing the analog input
voltage into a capacitance of 60 pF.
CS
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,
DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup
time.
DATA INPUT
17
I
Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next.
The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK.
After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order.
DATA OUT
16
O
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state
and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The
next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and
the remaining bits are shifted out in order.
EOC
19
O
End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and
remains low until the conversion is complete and the data is ready for transfer.
GND
10
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.
I/O CLOCK
18
I
Input/output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of the I/O
CLOCK.
3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of I/O CLOCK.
4. It transfers control of the conversion to the internal state controller on the falling edge of the last
I/O CLOCK.
REF+
14
I
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The
maximum input voltage range is determined by the difference between the voltage applied to this terminal and
the voltage applied to the REF– terminal.
REF–
13
I
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–.
VCC
MSB/LSB = Most significant bit /least significant bit
20
Positive supply voltage
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| TLC254ACD | 功能描述:運算放大器 - 運放 Quad LinCMOS RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| TLC254ACDG4 | 功能描述:運算放大器 - 運放 LinCMOS Quad OP AMP RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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